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eth: Add MAC statistics module to 10G MAC+PCS

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-09 12:18:42 -07:00
parent ddf1b37f4e
commit 93d9c8c9f6
11 changed files with 621 additions and 116 deletions
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5
tb/eth/taxi_eth_mac_phy_10g_fifo/Makefile
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@@ -46,6 +46,11 @@ export PARAM_RX_SERDES_PIPELINE := 2
export PARAM_BITSLIP_HIGH_CYCLES := 0
export PARAM_BITSLIP_LOW_CYCLES := 7
export PARAM_COUNT_125US := 195
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1

24
tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py
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@@ -52,6 +52,7 @@ class TB:
cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.ptp_sample_clk, 9.9, units="ns").start())
self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
@@ -61,12 +62,16 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.logic_clk)
dut.ptp_ts_step.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
@@ -75,16 +80,19 @@ class TB:
self.dut.logic_rst.setimmediatevalue(0)
self.dut.rx_rst.setimmediatevalue(0)
self.dut.tx_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
@@ -94,7 +102,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -152,7 +161,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -204,7 +214,8 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.axis_source.width // 8
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -411,6 +422,11 @@ def test_taxi_eth_mac_phy_10g_fifo(request, data_w, dic_en):
parameters['BITSLIP_HIGH_CYCLES'] = 0
parameters['BITSLIP_LOW_CYCLES'] = 7
parameters['COUNT_125US'] = int(1250/6.4)
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1

47
tb/eth/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv
View File

@@ -36,6 +36,11 @@ module test_taxi_eth_mac_phy_10g_fifo #
parameter BITSLIP_HIGH_CYCLES = 0,
parameter BITSLIP_LOW_CYCLES = 7,
parameter COUNT_125US = 125000/6.4,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -75,6 +80,13 @@ logic [HDR_W-1:0] serdes_rx_hdr;
logic serdes_rx_bitslip;
logic serdes_rx_reset_req;
logic [PTP_TS_W-1:0] ptp_ts;
logic ptp_ts_step;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
@@ -90,11 +102,10 @@ logic rx_fifo_overflow;
logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [PTP_TS_W-1:0] ptp_ts;
logic ptp_ts_step;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
logic cfg_tx_prbs31_enable;
logic cfg_rx_prbs31_enable;
@@ -116,6 +127,11 @@ taxi_eth_mac_phy_10g_fifo #(
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
@@ -160,6 +176,19 @@ uut (
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
/*
* PTP clock
*/
.ptp_ts(ptp_ts),
.ptp_ts_step(ptp_ts_step),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
@@ -178,17 +207,13 @@ uut (
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
/*
* PTP clock
*/
.ptp_ts(ptp_ts),
.ptp_ts_step(ptp_ts_step),
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)