From 93ef0f970b4bc41873af3947ea0f6aea5345e1d0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 4 Oct 2025 19:01:47 -0700 Subject: [PATCH] eth: Re-nest if statements for termination character handling in 10G RX logic Signed-off-by: Alex Forencich --- src/eth/rtl/taxi_axis_baser_rx_32.sv | 60 +++++++++++------------ src/eth/rtl/taxi_axis_baser_rx_64.sv | 72 ++++++++++++++-------------- src/eth/rtl/taxi_axis_xgmii_rx_32.sv | 60 +++++++++++------------ src/eth/rtl/taxi_axis_xgmii_rx_64.sv | 68 +++++++++++++------------- 4 files changed, 126 insertions(+), 134 deletions(-) diff --git a/src/eth/rtl/taxi_axis_baser_rx_32.sv b/src/eth/rtl/taxi_axis_baser_rx_32.sv index 62403a5..9c2af8d 100644 --- a/src/eth/rtl/taxi_axis_baser_rx_32.sv +++ b/src/eth/rtl/taxi_axis_baser_rx_32.sv @@ -437,42 +437,40 @@ always_comb begin stat_rx_pkt_jabber_next = frame_oversize_next; reset_crc = 1'b1; state_next = STATE_IDLE; - end else if (term_present_reg) begin - reset_crc = 1'b1; - if (term_first_cycle_reg) begin - // end this cycle - m_axis_rx_tkeep_next = 4'b1111; - m_axis_rx_tlast_next = 1'b1; - if (crc_valid_save[3]) begin - // CRC valid - if (frame_oversize_next) begin - // too long - m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_bad_next = 1'b1; - end else begin - // length OK - m_axis_rx_tuser_next = 1'b0; - stat_rx_pkt_good_next = 1'b1; - end - end else begin + end else if (term_first_cycle_reg) begin + // end this cycle + m_axis_rx_tkeep_next = 4'b1111; + m_axis_rx_tlast_next = 1'b1; + if (crc_valid_save[3]) begin + // CRC valid + if (frame_oversize_next) begin + // too long m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; - stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_bad_next = 1'b1; - stat_rx_err_bad_fcs_next = 1'b1; + end else begin + // length OK + m_axis_rx_tuser_next = 1'b0; + stat_rx_pkt_good_next = 1'b1; end - stat_rx_pkt_len_next = frame_len_next; - stat_rx_pkt_ucast_next = !is_mcast_reg; - stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; - stat_rx_pkt_bcast_next = is_bcast_reg; - stat_rx_pkt_vlan_next = is_8021q_reg; - stat_rx_err_oversize_next = frame_oversize_next; - stat_rx_err_preamble_next = !pre_ok_reg; - state_next = STATE_IDLE; end else begin - // need extra cycle - state_next = STATE_LAST; + m_axis_rx_tuser_next = 1'b1; + stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; + stat_rx_pkt_jabber_next = frame_oversize_next; + stat_rx_pkt_bad_next = 1'b1; + stat_rx_err_bad_fcs_next = 1'b1; end + stat_rx_pkt_len_next = frame_len_next; + stat_rx_pkt_ucast_next = !is_mcast_reg; + stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; + stat_rx_pkt_bcast_next = is_bcast_reg; + stat_rx_pkt_vlan_next = is_8021q_reg; + stat_rx_err_oversize_next = frame_oversize_next; + stat_rx_err_preamble_next = !pre_ok_reg; + reset_crc = 1'b1; + state_next = STATE_IDLE; + end else if (term_present_reg) begin + // need extra cycle + state_next = STATE_LAST; end else begin state_next = STATE_PAYLOAD; end diff --git a/src/eth/rtl/taxi_axis_baser_rx_64.sv b/src/eth/rtl/taxi_axis_baser_rx_64.sv index ec8816a..5668280 100644 --- a/src/eth/rtl/taxi_axis_baser_rx_64.sv +++ b/src/eth/rtl/taxi_axis_baser_rx_64.sv @@ -446,48 +446,46 @@ always_comb begin reset_crc = 1'b1; state_next = STATE_IDLE; - end if (term_present_reg) begin - if (term_first_cycle_reg) begin - // end this cycle - m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg); - m_axis_rx_tlast_next = 1'b1; - if ((term_lane_reg == 0 && crc_valid_save[7]) || - (term_lane_reg == 1 && crc_valid[0]) || - (term_lane_reg == 2 && crc_valid[1]) || - (term_lane_reg == 3 && crc_valid[2]) || - (term_lane_reg == 4 && crc_valid[3])) begin - // CRC valid - if (frame_oversize_next) begin - // too long - m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_bad_next = 1'b1; - end else begin - // length OK - m_axis_rx_tuser_next = 1'b0; - stat_rx_pkt_good_next = 1'b1; - end - end else begin + end else if (term_first_cycle_reg) begin + // end this cycle + m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg); + m_axis_rx_tlast_next = 1'b1; + if ((term_lane_reg == 0 && crc_valid_save[7]) || + (term_lane_reg == 1 && crc_valid[0]) || + (term_lane_reg == 2 && crc_valid[1]) || + (term_lane_reg == 3 && crc_valid[2]) || + (term_lane_reg == 4 && crc_valid[3])) begin + // CRC valid + if (frame_oversize_next) begin + // too long m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; - stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_bad_next = 1'b1; - stat_rx_err_bad_fcs_next = 1'b1; + end else begin + // length OK + m_axis_rx_tuser_next = 1'b0; + stat_rx_pkt_good_next = 1'b1; end - - stat_rx_pkt_len_next = frame_len_next; - stat_rx_pkt_ucast_next = !is_mcast_reg; - stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; - stat_rx_pkt_bcast_next = is_bcast_reg; - stat_rx_pkt_vlan_next = is_8021q_reg; - stat_rx_err_oversize_next = frame_oversize_next; - stat_rx_err_preamble_next = !pre_ok_reg; - - reset_crc = 1'b1; - state_next = STATE_IDLE; end else begin - // need extra cycle - state_next = STATE_LAST; + m_axis_rx_tuser_next = 1'b1; + stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; + stat_rx_pkt_jabber_next = frame_oversize_next; + stat_rx_pkt_bad_next = 1'b1; + stat_rx_err_bad_fcs_next = 1'b1; end + + stat_rx_pkt_len_next = frame_len_next; + stat_rx_pkt_ucast_next = !is_mcast_reg; + stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; + stat_rx_pkt_bcast_next = is_bcast_reg; + stat_rx_pkt_vlan_next = is_8021q_reg; + stat_rx_err_oversize_next = frame_oversize_next; + stat_rx_err_preamble_next = !pre_ok_reg; + + reset_crc = 1'b1; + state_next = STATE_IDLE; + end else if (term_present_reg) begin + // need extra cycle + state_next = STATE_LAST; end else begin state_next = STATE_PAYLOAD; end diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv index 1034e09..59f7c0c 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv @@ -395,42 +395,40 @@ always_comb begin stat_rx_pkt_jabber_next = frame_oversize_next; reset_crc = 1'b1; state_next = STATE_IDLE; - end else if (term_present_reg) begin - reset_crc = 1'b1; - if (term_first_cycle_reg) begin - // end this cycle - m_axis_rx_tkeep_next = 4'b1111; - m_axis_rx_tlast_next = 1'b1; - if (crc_valid_save[3]) begin - // CRC valid - if (frame_oversize_next) begin - // too long - m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_bad_next = 1'b1; - end else begin - // length OK - m_axis_rx_tuser_next = 1'b0; - stat_rx_pkt_good_next = 1'b1; - end - end else begin + end else if (term_first_cycle_reg) begin + // end this cycle + m_axis_rx_tkeep_next = 4'b1111; + m_axis_rx_tlast_next = 1'b1; + if (crc_valid_save[3]) begin + // CRC valid + if (frame_oversize_next) begin + // too long m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; - stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_bad_next = 1'b1; - stat_rx_err_bad_fcs_next = 1'b1; + end else begin + // length OK + m_axis_rx_tuser_next = 1'b0; + stat_rx_pkt_good_next = 1'b1; end - stat_rx_pkt_len_next = frame_len_next; - stat_rx_pkt_ucast_next = !is_mcast_reg; - stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; - stat_rx_pkt_bcast_next = is_bcast_reg; - stat_rx_pkt_vlan_next = is_8021q_reg; - stat_rx_err_oversize_next = frame_oversize_next; - stat_rx_err_preamble_next = !pre_ok_reg; - state_next = STATE_IDLE; end else begin - // need extra cycle - state_next = STATE_LAST; + m_axis_rx_tuser_next = 1'b1; + stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; + stat_rx_pkt_jabber_next = frame_oversize_next; + stat_rx_pkt_bad_next = 1'b1; + stat_rx_err_bad_fcs_next = 1'b1; end + stat_rx_pkt_len_next = frame_len_next; + stat_rx_pkt_ucast_next = !is_mcast_reg; + stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; + stat_rx_pkt_bcast_next = is_bcast_reg; + stat_rx_pkt_vlan_next = is_8021q_reg; + stat_rx_err_oversize_next = frame_oversize_next; + stat_rx_err_preamble_next = !pre_ok_reg; + reset_crc = 1'b1; + state_next = STATE_IDLE; + end else if (term_present_reg) begin + // need extra cycle + state_next = STATE_LAST; end else begin state_next = STATE_PAYLOAD; end diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv index 3423c8e..dbaec71 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv @@ -392,46 +392,44 @@ always_comb begin stat_rx_pkt_jabber_next = frame_oversize_next; reset_crc = 1'b1; state_next = STATE_IDLE; - end else if (term_present_reg) begin - reset_crc = 1'b1; - if (term_first_cycle_reg) begin - // end this cycle - m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); - m_axis_rx_tlast_next = 1'b1; - if ((term_lane_reg == 0 && crc_valid_save[7]) || - (term_lane_reg == 1 && crc_valid[0]) || - (term_lane_reg == 2 && crc_valid[1]) || - (term_lane_reg == 3 && crc_valid[2]) || - (term_lane_reg == 4 && crc_valid[3])) begin - // CRC valid - if (frame_oversize_next) begin - // too long - m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_bad_next = 1'b1; - end else begin - // length OK - m_axis_rx_tuser_next = 1'b0; - stat_rx_pkt_good_next = 1'b1; - end - end else begin + end else if (term_first_cycle_reg) begin + // end this cycle + m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); + m_axis_rx_tlast_next = 1'b1; + if ((term_lane_reg == 0 && crc_valid_save[7]) || + (term_lane_reg == 1 && crc_valid[0]) || + (term_lane_reg == 2 && crc_valid[1]) || + (term_lane_reg == 3 && crc_valid[2]) || + (term_lane_reg == 4 && crc_valid[3])) begin + // CRC valid + if (frame_oversize_next) begin + // too long m_axis_rx_tuser_next = 1'b1; - stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; - stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_bad_next = 1'b1; - stat_rx_err_bad_fcs_next = 1'b1; + end else begin + // length OK + m_axis_rx_tuser_next = 1'b0; + stat_rx_pkt_good_next = 1'b1; end - stat_rx_pkt_len_next = frame_len_next; - stat_rx_pkt_ucast_next = !is_mcast_reg; - stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; - stat_rx_pkt_bcast_next = is_bcast_reg; - stat_rx_pkt_vlan_next = is_8021q_reg; - stat_rx_err_oversize_next = frame_oversize_next; - stat_rx_err_preamble_next = !pre_ok_reg; - state_next = STATE_IDLE; end else begin - // need extra cycle - state_next = STATE_LAST; + m_axis_rx_tuser_next = 1'b1; + stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0; + stat_rx_pkt_jabber_next = frame_oversize_next; + stat_rx_pkt_bad_next = 1'b1; + stat_rx_err_bad_fcs_next = 1'b1; end + stat_rx_pkt_len_next = frame_len_next; + stat_rx_pkt_ucast_next = !is_mcast_reg; + stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg; + stat_rx_pkt_bcast_next = is_bcast_reg; + stat_rx_pkt_vlan_next = is_8021q_reg; + stat_rx_err_oversize_next = frame_oversize_next; + stat_rx_err_preamble_next = !pre_ok_reg; + reset_crc = 1'b1; + state_next = STATE_IDLE; + end else if (term_present_reg) begin + // need extra cycle + state_next = STATE_LAST; end else begin state_next = STATE_PAYLOAD; end