mirror of
https://github.com/fpganinja/taxi.git
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eth: Support UltraScale CMACE3 in 100G wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -51,7 +51,7 @@ Note that Zircon is still under active development and may not ready for product
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The Taxi transport library contains several Ethernet MAC and PCS variants, covering link rates from 10 Mbps to 25 Gbps. The MAC modules support LFC and PFC pause frames, PTP timestamping, frame length enforcement, FCS computation and verification, and statistics reporting. PTP TD leaf clocks and statistics collection components are also integrated, configurable via instance parameters. Wrappers for low-speed operation support MII, GMII, and RGMII PHY-attach protocols for use with an external PHY chip. Wrappers for 1000BASE-X and 10GBASE-R/25GBASE-R include device-specific transceiver instances for a fully-integrated solution. Logic is available for a 10G/25G MAC, 10G/25G PCS, and 10G/25G "fused" MAC+PCS, with reduced latency and resource consumption.
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The 100G MAC/PHY/GT wrapper for UltraScale+ supports the hard CMAC for 100G and GTY transceivers. Currently it only supports operation at 100Gbps, but integration of the 10G/25G MAC logic is planned to support runtime switching to lower link rates as well as breaking out the separate lanes. Support for the UltraScale CMAC is also planned.
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The 100G MAC/PHY/GT wrapper for UltraScale/UltraScale+ supports the hard CMAC for 100G and GTY transceivers. Currently it only supports operation at 100Gbps, but integration of the 10G/25G MAC logic is planned to support runtime switching to lower link rates as well as breaking out the separate lanes. The wrapper only enables RS-FEC on UltraScale+ as the CMACE4 provides RS-FEC support in the hard logic, while the UltraScale CMACE3 requires separately-licensed soft logic for RS-FEC.
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The 10G/25G MAC/PHY/GT wrapper for 7-series/UltraScale/UltraScale+ supports GTX, GTH, and GTY transceivers. On UltraScale and UltraScale+ devices, it can be configured for either a 32-bit or 64-bit datapath via the DATA_W parameter. The 32-bit datapath supports 10G only, while the 64-bit datapath can be used for either 10G or 25G. The core supports USXGMII for operation with NBASE-T PHYs and SFP modules (10M/100M/1G/2.5G/5G/10G), including dynamic detection of USXGMII modules. TCL scripts for generating the GT cores are provided for both 10G and 25G and for several common reference clocks. The core supports operation in either a normal latency mode or a low latency mode via the CFG_LOW_LATENCY paremter, which affects the clock frequency and transceiver configuration (async gearbox vs. sync gearbox and buffer bypass). The low latency mode has a slightly higher clock frequency and resource consumption, so it is not recommended unless you really need to shave off a new nanoseconds of latency, or you need highest possible time sync precision. On 7-series, the core only supports 32-bit low-latency mode. The wrapper also provides an APB interface for configuring the transceivers and QPLLs.
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@@ -161,7 +161,7 @@ The Taxi transport library contains many smaller components that can be composed
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* RGMII PHY interface
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* 1000BASE-X/SGMII MAC/PHY/GT wrapper for UltraScale/UltraScale+
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* 10G/25G/USXGMII MAC/PHY/GT wrapper for 7-series/UltraScale/UltraScale+
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* 100G MAC/PHY/GY wrapper for UltraScale+
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* 100G MAC/PHY/GY wrapper for UltraScale/UltraScale+
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* General input/output
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* Switch debouncer
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* LED shift register driver
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@@ -544,7 +544,7 @@ if (SIM) begin : cmac
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assign rx_status = !rx_rst_out[0];
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end else if (GT_USP) begin : cmac
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// UltraScale+ CMAC
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// UltraScale+ CMACE4
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taxi_eth_mac_100g_us_cmac cmac_inst (
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.txdata_in(cmac_txdata),
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@@ -905,8 +905,322 @@ end else if (GT_USP) begin : cmac
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);
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end else begin
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// UltraScale CMACE3
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$fatal(0, "Error: invalid configuration (%m)");
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taxi_eth_mac_100g_us_cmac cmac_inst (
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.txdata_in(cmac_txdata),
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.txctrl0_in(cmac_txctrl0),
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.txctrl1_in(cmac_txctrl1),
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.rxdata_out(cmac_rxdata),
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.rxctrl0_out(cmac_rxctrl0),
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.rxctrl1_out(cmac_rxctrl1),
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.rx_axis_tvalid(m_axis_rx.tvalid),
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.rx_axis_tdata(m_axis_rx.tdata),
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.rx_axis_tlast(m_axis_rx.tlast),
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.rx_axis_tkeep(m_axis_rx.tkeep),
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.rx_axis_tuser(m_axis_rx.tuser),
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.rx_lane_aligner_fill_0(),
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.rx_lane_aligner_fill_1(),
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.rx_lane_aligner_fill_2(),
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.rx_lane_aligner_fill_3(),
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.rx_lane_aligner_fill_4(),
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.rx_lane_aligner_fill_5(),
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.rx_lane_aligner_fill_6(),
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.rx_lane_aligner_fill_7(),
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.rx_lane_aligner_fill_8(),
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.rx_lane_aligner_fill_9(),
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.rx_lane_aligner_fill_10(),
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.rx_lane_aligner_fill_11(),
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.rx_lane_aligner_fill_12(),
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.rx_lane_aligner_fill_13(),
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.rx_lane_aligner_fill_14(),
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.rx_lane_aligner_fill_15(),
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.rx_lane_aligner_fill_16(),
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.rx_lane_aligner_fill_17(),
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.rx_lane_aligner_fill_18(),
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.rx_lane_aligner_fill_19(),
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.rx_ptp_tstamp_out(),//
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.rx_ptp_pcslane_out(),
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.ctl_rx_systemtimerin('0),
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.stat_rx_pause(stat_rx_lfc_pkt),
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.stat_rx_pause_quanta0(),
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.stat_rx_pause_quanta1(),
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.stat_rx_pause_quanta2(),
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.stat_rx_pause_quanta3(),
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.stat_rx_pause_quanta4(),
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.stat_rx_pause_quanta5(),
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.stat_rx_pause_quanta6(),
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.stat_rx_pause_quanta7(),
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.stat_rx_pause_quanta8(),
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.stat_rx_pause_req({rx_lfc_req, rx_pfc_req}),
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.stat_rx_pause_valid(),
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.stat_rx_user_pause(stat_rx_pfc_pkt),
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.ctl_rx_check_etype_gcp(1'b1),
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.ctl_rx_check_etype_gpp(1'b1),
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.ctl_rx_check_etype_pcp(1'b1),
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.ctl_rx_check_etype_ppp(1'b1),
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.ctl_rx_check_mcast_gcp(cfg_mcf_rx_check_eth_dst_mcast),
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.ctl_rx_check_mcast_gpp(cfg_mcf_rx_check_eth_dst_mcast),
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.ctl_rx_check_mcast_pcp(cfg_mcf_rx_check_eth_dst_mcast),
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.ctl_rx_check_mcast_ppp(cfg_mcf_rx_check_eth_dst_mcast),
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.ctl_rx_check_opcode_gcp(cfg_mcf_rx_check_opcode_lfc),
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.ctl_rx_check_opcode_gpp(cfg_mcf_rx_check_opcode_lfc),
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.ctl_rx_check_opcode_pcp(cfg_mcf_rx_check_opcode_pfc),
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.ctl_rx_check_opcode_ppp(cfg_mcf_rx_check_opcode_pfc),
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.ctl_rx_check_sa_gcp(cfg_mcf_rx_check_eth_src),
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.ctl_rx_check_sa_gpp(cfg_mcf_rx_check_eth_src),
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.ctl_rx_check_sa_pcp(cfg_mcf_rx_check_eth_src),
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.ctl_rx_check_sa_ppp(cfg_mcf_rx_check_eth_src),
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.ctl_rx_check_ucast_gcp(cfg_mcf_rx_check_eth_dst_ucast),
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.ctl_rx_check_ucast_gpp(cfg_mcf_rx_check_eth_dst_ucast),
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.ctl_rx_check_ucast_pcp(cfg_mcf_rx_check_eth_dst_ucast),
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.ctl_rx_check_ucast_ppp(cfg_mcf_rx_check_eth_dst_ucast),
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.ctl_rx_enable_gcp(cfg_rx_lfc_en && PAUSE_EN),
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.ctl_rx_enable_gpp(cfg_rx_lfc_en && PAUSE_EN),
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.ctl_rx_enable_pcp(cfg_rx_pfc_en != 0 && PFC_EN),
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.ctl_rx_enable_ppp(cfg_rx_pfc_en != 0 && PFC_EN),
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.ctl_rx_pause_ack({rx_lfc_ack, rx_pfc_ack}),
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.ctl_rx_pause_enable({rx_lfc_en & PAUSE_EN, rx_pfc_en & {8{PFC_EN}}}),
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.ctl_rx_enable(cfg_rx_enable),
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.ctl_rx_force_resync('0),
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.ctl_rx_test_pattern('0),
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.rx_clk(rx_clk[0]),
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.stat_rx_aligned(),
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.stat_rx_aligned_err(),
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.stat_rx_bad_code(),
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.stat_rx_bad_fcs(),
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.stat_rx_bad_preamble(),
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.stat_rx_bad_sfd(),
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.stat_rx_bip_err_0(),
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.stat_rx_bip_err_1(),
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.stat_rx_bip_err_2(),
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.stat_rx_bip_err_3(),
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.stat_rx_bip_err_4(),
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.stat_rx_bip_err_5(),
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.stat_rx_bip_err_6(),
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.stat_rx_bip_err_7(),
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.stat_rx_bip_err_8(),
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.stat_rx_bip_err_9(),
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.stat_rx_bip_err_10(),
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.stat_rx_bip_err_11(),
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.stat_rx_bip_err_12(),
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.stat_rx_bip_err_13(),
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.stat_rx_bip_err_14(),
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.stat_rx_bip_err_15(),
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.stat_rx_bip_err_16(),
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.stat_rx_bip_err_17(),
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.stat_rx_bip_err_18(),
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.stat_rx_bip_err_19(),
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.stat_rx_block_lock(rx_block_lock),
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.stat_rx_broadcast(stat_rx_pkt_bcast),
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.stat_rx_fragment(stat_rx_pkt_fragment),
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.stat_rx_framing_err_0(),
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.stat_rx_framing_err_1(),
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.stat_rx_framing_err_2(),
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.stat_rx_framing_err_3(),
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.stat_rx_framing_err_4(),
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.stat_rx_framing_err_5(),
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.stat_rx_framing_err_6(),
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.stat_rx_framing_err_7(),
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.stat_rx_framing_err_8(),
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.stat_rx_framing_err_9(),
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.stat_rx_framing_err_10(),
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.stat_rx_framing_err_11(),
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.stat_rx_framing_err_12(),
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.stat_rx_framing_err_13(),
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.stat_rx_framing_err_14(),
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.stat_rx_framing_err_15(),
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.stat_rx_framing_err_16(),
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.stat_rx_framing_err_17(),
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.stat_rx_framing_err_18(),
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.stat_rx_framing_err_19(),
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.stat_rx_framing_err_valid_0(),
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.stat_rx_framing_err_valid_1(),
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.stat_rx_framing_err_valid_2(),
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.stat_rx_framing_err_valid_3(),
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.stat_rx_framing_err_valid_4(),
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.stat_rx_framing_err_valid_5(),
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.stat_rx_framing_err_valid_6(),
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.stat_rx_framing_err_valid_7(),
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.stat_rx_framing_err_valid_8(),
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.stat_rx_framing_err_valid_9(),
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.stat_rx_framing_err_valid_10(),
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.stat_rx_framing_err_valid_11(),
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.stat_rx_framing_err_valid_12(),
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.stat_rx_framing_err_valid_13(),
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.stat_rx_framing_err_valid_14(),
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.stat_rx_framing_err_valid_15(),
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.stat_rx_framing_err_valid_16(),
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.stat_rx_framing_err_valid_17(),
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.stat_rx_framing_err_valid_18(),
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.stat_rx_framing_err_valid_19(),
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.stat_rx_got_signal_os(),
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.stat_rx_hi_ber(rx_high_ber),
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.stat_rx_inrangeerr(),
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.stat_rx_internal_local_fault(),
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.stat_rx_jabber(stat_rx_pkt_jabber),
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.stat_rx_local_fault(),
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.stat_rx_mf_err(),
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.stat_rx_mf_len_err(),
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.stat_rx_mf_repeat_err(),
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.stat_rx_misaligned(),
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.stat_rx_multicast(stat_rx_pkt_mcast),
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.stat_rx_oversize(stat_rx_err_oversize),
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.stat_rx_packet_64_bytes(),
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.stat_rx_packet_65_127_bytes(),
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.stat_rx_packet_128_255_bytes(),
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.stat_rx_packet_256_511_bytes(),
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.stat_rx_packet_512_1023_bytes(),
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.stat_rx_packet_1024_1518_bytes(),
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.stat_rx_packet_1519_1522_bytes(),
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.stat_rx_packet_1523_1548_bytes(),
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.stat_rx_packet_1549_2047_bytes(),
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.stat_rx_packet_2048_4095_bytes(),
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.stat_rx_packet_4096_8191_bytes(),
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.stat_rx_packet_8192_9215_bytes(),
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.stat_rx_packet_bad_fcs(stat_rx_err_bad_fcs),
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.stat_rx_packet_large(),
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.stat_rx_packet_small(),
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.stat_rx_received_local_fault(),
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.stat_rx_remote_fault(),
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.stat_rx_status(rx_status),
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.stat_rx_stomped_fcs(),
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.stat_rx_synced(),
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.stat_rx_synced_err(),
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.stat_rx_test_pattern_mismatch(),
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.stat_rx_toolong(),
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.stat_rx_total_bytes(stat_rx_byte),
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.stat_rx_total_good_bytes(stat_rx_pkt_len),
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.stat_rx_total_good_packets(stat_rx_pkt_good),
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.stat_rx_total_packets(),
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.stat_rx_truncated(),
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.stat_rx_undersize(),
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.stat_rx_unicast(stat_rx_pkt_ucast),
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.stat_rx_vlan(stat_rx_pkt_vlan),
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||||
.stat_rx_pcsl_demuxed(),
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.stat_rx_pcsl_number_0(),
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.stat_rx_pcsl_number_1(),
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||||
.stat_rx_pcsl_number_2(),
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||||
.stat_rx_pcsl_number_3(),
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.stat_rx_pcsl_number_4(),
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||||
.stat_rx_pcsl_number_5(),
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.stat_rx_pcsl_number_6(),
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.stat_rx_pcsl_number_7(),
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||||
.stat_rx_pcsl_number_8(),
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||||
.stat_rx_pcsl_number_9(),
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.stat_rx_pcsl_number_10(),
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.stat_rx_pcsl_number_11(),
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.stat_rx_pcsl_number_12(),
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||||
.stat_rx_pcsl_number_13(),
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||||
.stat_rx_pcsl_number_14(),
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||||
.stat_rx_pcsl_number_15(),
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||||
.stat_rx_pcsl_number_16(),
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||||
.stat_rx_pcsl_number_17(),
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||||
.stat_rx_pcsl_number_18(),
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||||
.stat_rx_pcsl_number_19(),
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||||
|
||||
.ctl_tx_systemtimerin('0),
|
||||
.stat_tx_ptp_fifo_read_error(),
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||||
.stat_tx_ptp_fifo_write_error(),
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||||
.tx_ptp_tstamp_valid_out(), //
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||||
.tx_ptp_pcslane_out(),
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||||
.tx_ptp_tstamp_tag_out(), //
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||||
.tx_ptp_tstamp_out(), //
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||||
.tx_ptp_1588op_in(2'b10),
|
||||
.tx_ptp_tag_field_in('0), //
|
||||
|
||||
.stat_tx_bad_fcs(),
|
||||
.stat_tx_broadcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_frame_error(stat_tx_err_user),
|
||||
.stat_tx_local_fault(),
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||||
.stat_tx_multicast(stat_tx_pkt_mcast),
|
||||
.stat_tx_packet_64_bytes(),
|
||||
.stat_tx_packet_65_127_bytes(),
|
||||
.stat_tx_packet_128_255_bytes(),
|
||||
.stat_tx_packet_256_511_bytes(),
|
||||
.stat_tx_packet_512_1023_bytes(),
|
||||
.stat_tx_packet_1024_1518_bytes(),
|
||||
.stat_tx_packet_1519_1522_bytes(),
|
||||
.stat_tx_packet_1523_1548_bytes(),
|
||||
.stat_tx_packet_1549_2047_bytes(),
|
||||
.stat_tx_packet_2048_4095_bytes(),
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||||
.stat_tx_packet_4096_8191_bytes(),
|
||||
.stat_tx_packet_8192_9215_bytes(),
|
||||
.stat_tx_packet_large(),
|
||||
.stat_tx_packet_small(),
|
||||
.stat_tx_total_bytes(stat_tx_byte),
|
||||
.stat_tx_total_good_bytes(stat_tx_pkt_len),
|
||||
.stat_tx_total_good_packets(stat_tx_pkt_good),
|
||||
.stat_tx_total_packets(),
|
||||
.stat_tx_unicast(stat_tx_pkt_ucast),
|
||||
.stat_tx_vlan(stat_tx_pkt_vlan),
|
||||
|
||||
.ctl_tx_enable(cfg_tx_enable),
|
||||
.ctl_tx_send_idle('0),
|
||||
.ctl_tx_send_rfi('0),
|
||||
.ctl_tx_test_pattern('0),
|
||||
|
||||
.tx_clk(tx_clk[0]),
|
||||
|
||||
.stat_tx_pause_valid(),
|
||||
.stat_tx_pause(stat_tx_lfc_pkt),
|
||||
.stat_tx_user_pause(stat_tx_pfc_pkt),
|
||||
|
||||
.ctl_tx_pause_enable({cfg_tx_lfc_en & PAUSE_EN, cfg_tx_pfc_en & {8{PFC_EN}}}),
|
||||
.ctl_tx_pause_quanta0(cfg_tx_pfc_quanta[0]),
|
||||
.ctl_tx_pause_quanta1(cfg_tx_pfc_quanta[1]),
|
||||
.ctl_tx_pause_quanta2(cfg_tx_pfc_quanta[2]),
|
||||
.ctl_tx_pause_quanta3(cfg_tx_pfc_quanta[3]),
|
||||
.ctl_tx_pause_quanta4(cfg_tx_pfc_quanta[4]),
|
||||
.ctl_tx_pause_quanta5(cfg_tx_pfc_quanta[5]),
|
||||
.ctl_tx_pause_quanta6(cfg_tx_pfc_quanta[6]),
|
||||
.ctl_tx_pause_quanta7(cfg_tx_pfc_quanta[7]),
|
||||
.ctl_tx_pause_quanta8(cfg_tx_lfc_quanta),
|
||||
.ctl_tx_pause_refresh_timer0(cfg_tx_pfc_refresh[0]),
|
||||
.ctl_tx_pause_refresh_timer1(cfg_tx_pfc_refresh[1]),
|
||||
.ctl_tx_pause_refresh_timer2(cfg_tx_pfc_refresh[2]),
|
||||
.ctl_tx_pause_refresh_timer3(cfg_tx_pfc_refresh[3]),
|
||||
.ctl_tx_pause_refresh_timer4(cfg_tx_pfc_refresh[4]),
|
||||
.ctl_tx_pause_refresh_timer5(cfg_tx_pfc_refresh[5]),
|
||||
.ctl_tx_pause_refresh_timer6(cfg_tx_pfc_refresh[6]),
|
||||
.ctl_tx_pause_refresh_timer7(cfg_tx_pfc_refresh[7]),
|
||||
.ctl_tx_pause_refresh_timer8(cfg_tx_lfc_refresh),
|
||||
.ctl_tx_pause_req({tx_lfc_req, tx_pfc_req}),
|
||||
.ctl_tx_resend_pause(tx_lfc_resend | tx_pfc_resend),
|
||||
|
||||
.tx_axis_tready(axis_tx_pad.tready),
|
||||
.tx_axis_tvalid(axis_tx_pad.tvalid),
|
||||
.tx_axis_tdata(axis_tx_pad.tdata),
|
||||
.tx_axis_tlast(axis_tx_pad.tlast),
|
||||
.tx_axis_tkeep(axis_tx_pad.tkeep),
|
||||
.tx_axis_tuser(axis_tx_pad.tuser[0]),
|
||||
|
||||
.tx_ovfout(),
|
||||
.tx_unfout(),
|
||||
|
||||
.tx_reset_done(tx_rst_out[0]),
|
||||
.rx_reset_done(rx_rst_out[0]),
|
||||
|
||||
.rx_serdes_reset_done({6'h3f, rx_rst_out[3], rx_rst_out[2], rx_rst_out[1], rx_rst_out[0]}),
|
||||
.rx_serdes_clk_in({6'd0, rx_clk[3], rx_clk[2], rx_clk[1], rx_clk[0]}),
|
||||
|
||||
.drp_clk('0),
|
||||
.drp_addr('0),
|
||||
.drp_di('0),
|
||||
.drp_en('0),
|
||||
.drp_we('0),
|
||||
.drp_do(),
|
||||
.drp_rdy()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
|
||||
30
src/eth/rtl/us/taxi_eth_mac_100g_us_cmace3.tcl
Normal file
30
src/eth/rtl/us/taxi_eth_mac_100g_us_cmace3.tcl
Normal file
@@ -0,0 +1,30 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_mac_100g_us_cmac}
|
||||
|
||||
create_ip -name cmac -vendor xilinx.com -library ip -module_name $base_name
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.CMAC_CAUI4_MODE {1} \
|
||||
CONFIG.NUM_LANES {4} \
|
||||
CONFIG.USER_INTERFACE {AXIS} \
|
||||
CONFIG.GT_DRP_CLK {125} \
|
||||
CONFIG.GT_LOCATION {0} \
|
||||
CONFIG.TX_FLOW_CONTROL {1} \
|
||||
CONFIG.RX_FLOW_CONTROL {1} \
|
||||
CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
|
||||
CONFIG.RX_CHECK_ACK {1} \
|
||||
CONFIG.ENABLE_TIME_STAMPING {1} \
|
||||
CONFIG.PTP_TRANSPCLK_MODE {1}
|
||||
] [get_ips $base_name]
|
||||
|
||||
# disable LOC constraint
|
||||
set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips $base_name]]]
|
||||
generate_target synthesis [get_files [get_property IP_FILE [get_ips $base_name]]]
|
||||
set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips $base_name]]] $base_name.xdc]
|
||||
Reference in New Issue
Block a user