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dma: Add AXI central DMA module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-11-03 11:42:04 -08:00
parent 999602cf11
commit 9442bb7fbb
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README.md
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@@ -63,6 +63,7 @@ To facilitate the dual-license model, contributions to the project can only be a
* Direct Memory Access
* SV interface for segmented RAM
* SV interface for DMA descriptors
* AXI central DMA
* Segmented SDP RAM
* Segmented dual-clock SDP RAM
* Ethernet