From 94a821192c92f4df04f06871cb3f58a49b14f9c8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 30 Aug 2025 21:10:08 -0700 Subject: [PATCH] axi: Add AXI width converter module and testbench Signed-off-by: Alex Forencich --- README.md | 1 + src/axi/rtl/taxi_axi_adapter.f | 4 + src/axi/rtl/taxi_axi_adapter.sv | 82 ++ src/axi/rtl/taxi_axi_adapter_rd.sv | 813 ++++++++++++++++ src/axi/rtl/taxi_axi_adapter_wr.sv | 904 ++++++++++++++++++ src/axi/tb/taxi_axi_adapter/Makefile | 70 ++ .../taxi_axi_adapter/test_taxi_axi_adapter.py | 263 +++++ .../taxi_axi_adapter/test_taxi_axi_adapter.sv | 104 ++ 8 files changed, 2241 insertions(+) create mode 100644 src/axi/rtl/taxi_axi_adapter.f create mode 100644 src/axi/rtl/taxi_axi_adapter.sv create mode 100644 src/axi/rtl/taxi_axi_adapter_rd.sv create mode 100644 src/axi/rtl/taxi_axi_adapter_wr.sv create mode 100644 src/axi/tb/taxi_axi_adapter/Makefile create mode 100644 src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.py create mode 100644 src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.sv diff --git a/README.md b/README.md index 238f1d7..f831093 100644 --- a/README.md +++ b/README.md @@ -27,6 +27,7 @@ To facilitate the dual-license model, contributions to the project can only be a * AXI * SV interface for AXI * Register slice + * Width converter * Single-port RAM * AXI lite * SV interface for AXI lite diff --git a/src/axi/rtl/taxi_axi_adapter.f b/src/axi/rtl/taxi_axi_adapter.f new file mode 100644 index 0000000..b8da3e5 --- /dev/null +++ b/src/axi/rtl/taxi_axi_adapter.f @@ -0,0 +1,4 @@ +taxi_axi_adapter.sv +taxi_axi_adapter_wr.sv +taxi_axi_adapter_rd.sv +taxi_axi_if.sv diff --git a/src/axi/rtl/taxi_axi_adapter.sv b/src/axi/rtl/taxi_axi_adapter.sv new file mode 100644 index 0000000..c483440 --- /dev/null +++ b/src/axi/rtl/taxi_axi_adapter.sv @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 width adapter + */ +module taxi_axi_adapter # +( + // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible + parameter logic CONVERT_BURST = 1'b1, + // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible + parameter logic CONVERT_NARROW_BURST = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interface + */ + taxi_axi_if.wr_slv s_axi_wr, + taxi_axi_if.rd_slv s_axi_rd, + + /* + * AXI4 master interface + */ + taxi_axi_if.wr_mst m_axi_wr, + taxi_axi_if.rd_mst m_axi_rd +); + +taxi_axi_adapter_wr #( + .CONVERT_BURST(CONVERT_BURST), + .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST) +) +axi_adapter_wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_wr(s_axi_wr), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi_wr) +); + +taxi_axi_adapter_rd #( + .CONVERT_BURST(CONVERT_BURST), + .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST) +) +axi_adapter_rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_rd(s_axi_rd), + + /* + * AXI4 master interface + */ + .m_axi_rd(m_axi_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axi_adapter_rd.sv b/src/axi/rtl/taxi_axi_adapter_rd.sv new file mode 100644 index 0000000..3da9285 --- /dev/null +++ b/src/axi/rtl/taxi_axi_adapter_rd.sv @@ -0,0 +1,813 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 width adapter + */ +module taxi_axi_adapter_rd # +( + // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible + parameter logic CONVERT_BURST = 1'b1, + // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible + parameter logic CONVERT_NARROW_BURST = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interface + */ + taxi_axi_if.rd_slv s_axi_rd, + + /* + * AXI4 master interface + */ + taxi_axi_if.rd_mst m_axi_rd +); + +// extract parameters +localparam S_DATA_W = s_axi_rd.DATA_W; +localparam ADDR_W = s_axi_rd.ADDR_W; +localparam CL_ADDR_W = $clog2(ADDR_W); +localparam S_STRB_W = s_axi_rd.STRB_W; +localparam ID_W = s_axi_rd.ID_W; +localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axi_rd.ARUSER_EN; +localparam ARUSER_W = s_axi_rd.ARUSER_W; +localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN; +localparam RUSER_W = s_axi_rd.RUSER_W; + +localparam M_DATA_W = m_axi_rd.DATA_W; +localparam M_STRB_W = m_axi_rd.STRB_W; + +localparam S_ADDR_BIT_OFFSET = $clog2(S_STRB_W); +localparam M_ADDR_BIT_OFFSET = $clog2(M_STRB_W); +localparam S_BYTE_LANES = S_STRB_W; +localparam M_BYTE_LANES = M_STRB_W; +localparam S_BYTE_SIZE = S_DATA_W/S_BYTE_LANES; +localparam M_BYTE_SIZE = M_DATA_W/M_BYTE_LANES; +localparam logic [2:0] S_BURST_SIZE = 3'($clog2(S_STRB_W)); +localparam logic [2:0] M_BURST_SIZE = 3'($clog2(M_STRB_W)); + +// check configuration +if (S_BYTE_SIZE * S_STRB_W != S_DATA_W) + $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)"); + +if (M_BYTE_SIZE * M_STRB_W != M_DATA_W) + $fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)"); + +if (S_BYTE_SIZE != M_BYTE_SIZE) + $fatal(0, "Error: byte size mismatch (instance %m)"); + +if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES) + $fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)"); + +if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES) + $fatal(0, "Error: AXI master interface byte lane count must be even power of two (instance %m)"); + +if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass + // same width; bypass + + assign m_axi_rd.arid = s_axi_rd.arid; + assign m_axi_rd.araddr = s_axi_rd.araddr; + assign m_axi_rd.arlen = s_axi_rd.arlen; + assign m_axi_rd.arsize = s_axi_rd.arsize; + assign m_axi_rd.arburst = s_axi_rd.arburst; + assign m_axi_rd.arlock = s_axi_rd.arlock; + assign m_axi_rd.arcache = s_axi_rd.arcache; + assign m_axi_rd.arprot = s_axi_rd.arprot; + assign m_axi_rd.arqos = s_axi_rd.arqos; + assign m_axi_rd.arregion = s_axi_rd.arregion; + assign m_axi_rd.aruser = ARUSER_EN ? s_axi_rd.aruser : '0; + assign m_axi_rd.arvalid = s_axi_rd.arvalid; + assign s_axi_rd.arready = m_axi_rd.arready; + + assign s_axi_rd.rid = m_axi_rd.rid; + assign s_axi_rd.rdata = m_axi_rd.rdata; + assign s_axi_rd.rresp = m_axi_rd.rresp; + assign s_axi_rd.rlast = m_axi_rd.rlast; + assign s_axi_rd.ruser = RUSER_EN ? m_axi_rd.ruser : '0; + assign s_axi_rd.rvalid = m_axi_rd.rvalid; + assign m_axi_rd.rready = s_axi_rd.rready; + +end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize + // output is wider; upsize + + // output bus is wider + localparam EXPAND = M_BYTE_LANES > S_BYTE_LANES; + localparam DATA_W = EXPAND ? M_DATA_W : S_DATA_W; + localparam STRB_W = EXPAND ? M_STRB_W : S_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = EXPAND ? (M_BYTE_LANES / S_BYTE_LANES) : (S_BYTE_LANES / M_BYTE_LANES); + localparam CL_SEG_COUNT = $clog2(SEG_COUNT); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [1:0] + STATE_IDLE = 2'd0, + STATE_DATA = 2'd1, + STATE_DATA_READ = 2'd2, + STATE_DATA_SPLIT = 2'd3; + + logic [1:0] state_reg = STATE_IDLE, state_next; + + logic [ID_W-1:0] id_reg = '0, id_next; + logic [ADDR_W-1:0] addr_reg = '0, addr_next; + logic [DATA_W-1:0] data_reg = '0, data_next; + logic [1:0] resp_reg = '0, resp_next; + logic [RUSER_W-1:0] ruser_reg = '0, ruser_next; + logic [7:0] burst_reg = '0, burst_next; + logic [2:0] burst_size_reg = '0, burst_size_next; + logic [7:0] master_burst_reg = '0, master_burst_next; + logic [2:0] master_burst_size_reg = '0, master_burst_size_next; + + logic s_axi_arready_reg = 1'b0, s_axi_arready_next; + + logic [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next; + logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next; + logic [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next; + logic [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next; + logic [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next; + logic m_axi_arlock_reg = '0, m_axi_arlock_next; + logic [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next; + logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next; + logic [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next; + logic [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next; + logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next; + logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; + logic m_axi_rready_reg = 1'b0, m_axi_rready_next; + + // internal datapath + logic [ID_W-1:0] s_axi_rid_int; + logic [S_DATA_W-1:0] s_axi_rdata_int; + logic [1:0] s_axi_rresp_int; + logic s_axi_rlast_int; + logic [RUSER_W-1:0] s_axi_ruser_int; + logic s_axi_rvalid_int; + logic s_axi_rready_int_reg = 1'b0; + wire s_axi_rready_int_early; + + assign s_axi_rd.arready = s_axi_arready_reg; + + assign m_axi_rd.arid = '0; + assign m_axi_rd.araddr = m_axi_araddr_reg; + assign m_axi_rd.arlen = m_axi_arlen_reg; + assign m_axi_rd.arsize = m_axi_arsize_reg; + assign m_axi_rd.arburst = m_axi_arburst_reg; + assign m_axi_rd.arlock = m_axi_arlock_reg; + assign m_axi_rd.arcache = m_axi_arcache_reg; + assign m_axi_rd.arprot = m_axi_arprot_reg; + assign m_axi_rd.arqos = m_axi_arqos_reg; + assign m_axi_rd.arregion = m_axi_arregion_reg; + assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0; + assign m_axi_rd.arvalid = m_axi_arvalid_reg; + assign m_axi_rd.rready = m_axi_rready_reg; + + always_comb begin + state_next = STATE_IDLE; + + id_next = id_reg; + addr_next = addr_reg; + data_next = data_reg; + resp_next = resp_reg; + ruser_next = ruser_reg; + burst_next = burst_reg; + burst_size_next = burst_size_reg; + master_burst_next = master_burst_reg; + master_burst_size_next = master_burst_size_reg; + + s_axi_arready_next = 1'b0; + m_axi_arid_next = m_axi_arid_reg; + m_axi_araddr_next = m_axi_araddr_reg; + m_axi_arlen_next = m_axi_arlen_reg; + m_axi_arsize_next = m_axi_arsize_reg; + m_axi_arburst_next = m_axi_arburst_reg; + m_axi_arlock_next = m_axi_arlock_reg; + m_axi_arcache_next = m_axi_arcache_reg; + m_axi_arprot_next = m_axi_arprot_reg; + m_axi_arqos_next = m_axi_arqos_reg; + m_axi_arregion_next = m_axi_arregion_reg; + m_axi_aruser_next = m_axi_aruser_reg; + m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_rd.arready; + m_axi_rready_next = 1'b0; + + s_axi_rid_int = id_reg; + s_axi_rdata_int = m_axi_rd.rdata[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W]; + s_axi_rresp_int = m_axi_rd.rresp; + s_axi_rlast_int = m_axi_rd.rlast; + s_axi_ruser_int = m_axi_rd.ruser; + s_axi_rvalid_int = 1'b0; + + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_arready_next = !m_axi_rd.arvalid; + + if (s_axi_rd.arready && s_axi_rd.arvalid) begin + s_axi_arready_next = 1'b0; + id_next = s_axi_rd.arid; + m_axi_arid_next = s_axi_rd.arid; + m_axi_araddr_next = s_axi_rd.araddr; + addr_next = s_axi_rd.araddr; + burst_next = s_axi_rd.arlen; + burst_size_next = s_axi_rd.arsize; + if (CONVERT_BURST && s_axi_rd.arcache[1] && (CONVERT_NARROW_BURST || s_axi_rd.arsize == S_BURST_SIZE)) begin + // split reads + // require CONVERT_BURST and arcache[1] set + master_burst_size_next = M_BURST_SIZE; + if (CONVERT_NARROW_BURST) begin + m_axi_arlen_next = 8'((({8'd0, s_axi_rd.arlen} << s_axi_rd.arsize) + 16'(s_axi_rd.araddr[M_ADDR_BIT_OFFSET-1:0])) >> M_BURST_SIZE); + end else begin + m_axi_arlen_next = (s_axi_rd.arlen + 8'(s_axi_rd.araddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET])) >> CL_SEG_COUNT; + end + m_axi_arsize_next = M_BURST_SIZE; + state_next = STATE_DATA_READ; + end else begin + // output narrow burst + master_burst_size_next = s_axi_rd.arsize; + m_axi_arlen_next = s_axi_rd.arlen; + m_axi_arsize_next = s_axi_rd.arsize; + state_next = STATE_DATA; + end + m_axi_arburst_next = s_axi_rd.arburst; + m_axi_arlock_next = s_axi_rd.arlock; + m_axi_arcache_next = s_axi_rd.arcache; + m_axi_arprot_next = s_axi_rd.arprot; + m_axi_arqos_next = s_axi_rd.arqos; + m_axi_arregion_next = s_axi_rd.arregion; + m_axi_aruser_next = s_axi_rd.aruser; + m_axi_arvalid_next = 1'b1; + m_axi_rready_next = s_axi_rready_int_early; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_axi_rready_next = s_axi_rready_int_early; + + if (m_axi_rd.rready && m_axi_rd.rvalid) begin + s_axi_rid_int = id_reg; + s_axi_rdata_int = m_axi_rd.rdata[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W]; + s_axi_rresp_int = m_axi_rd.rresp; + s_axi_rlast_int = m_axi_rd.rlast; + s_axi_ruser_int = m_axi_rd.ruser; + s_axi_rvalid_int = 1'b1; + addr_next = addr_reg + (1 << burst_size_reg); + if (m_axi_rd.rlast) begin + m_axi_rready_next = 1'b0; + s_axi_arready_next = !m_axi_rd.arvalid; + state_next = STATE_IDLE; + end else begin + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + STATE_DATA_READ: begin + m_axi_rready_next = s_axi_rready_int_early; + + if (m_axi_rd.rready && m_axi_rd.rvalid) begin + s_axi_rid_int = id_reg; + data_next = m_axi_rd.rdata; + resp_next = m_axi_rd.rresp; + ruser_next = m_axi_rd.ruser; + s_axi_rdata_int = m_axi_rd.rdata[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W]; + s_axi_rresp_int = m_axi_rd.rresp; + s_axi_rlast_int = 1'b0; + s_axi_ruser_int = m_axi_rd.ruser; + s_axi_rvalid_int = 1'b1; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0) begin + m_axi_rready_next = 1'b0; + s_axi_arready_next = !m_axi_rd.arvalid; + s_axi_rlast_int = 1'b1; + state_next = STATE_IDLE; + end else if (addr_next[CL_ADDR_W'(master_burst_size_reg)] != addr_reg[CL_ADDR_W'(master_burst_size_reg)]) begin + state_next = STATE_DATA_READ; + end else begin + m_axi_rready_next = 1'b0; + state_next = STATE_DATA_SPLIT; + end + end else begin + state_next = STATE_DATA_READ; + end + end + STATE_DATA_SPLIT: begin + m_axi_rready_next = 1'b0; + + if (s_axi_rready_int_reg) begin + s_axi_rid_int = id_reg; + s_axi_rdata_int = data_reg[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W]; + s_axi_rresp_int = resp_reg; + s_axi_rlast_int = 1'b0; + s_axi_ruser_int = ruser_reg; + s_axi_rvalid_int = 1'b1; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (burst_reg == 0) begin + s_axi_arready_next = !m_axi_rd.arvalid; + s_axi_rlast_int = 1'b1; + state_next = STATE_IDLE; + end else if (addr_next[CL_ADDR_W'(master_burst_size_reg)] != addr_reg[CL_ADDR_W'(master_burst_size_reg)]) begin + m_axi_rready_next = s_axi_rready_int_early; + state_next = STATE_DATA_READ; + end else begin + state_next = STATE_DATA_SPLIT; + end + end else begin + state_next = STATE_DATA_SPLIT; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + id_reg <= id_next; + addr_reg <= addr_next; + data_reg <= data_next; + resp_reg <= resp_next; + ruser_reg <= ruser_next; + burst_reg <= burst_next; + burst_size_reg <= burst_size_next; + master_burst_reg <= master_burst_next; + master_burst_size_reg <= master_burst_size_next; + + s_axi_arready_reg <= s_axi_arready_next; + + m_axi_arid_reg <= m_axi_arid_next; + m_axi_araddr_reg <= m_axi_araddr_next; + m_axi_arlen_reg <= m_axi_arlen_next; + m_axi_arsize_reg <= m_axi_arsize_next; + m_axi_arburst_reg <= m_axi_arburst_next; + m_axi_arlock_reg <= m_axi_arlock_next; + m_axi_arcache_reg <= m_axi_arcache_next; + m_axi_arprot_reg <= m_axi_arprot_next; + m_axi_arqos_reg <= m_axi_arqos_next; + m_axi_arregion_reg <= m_axi_arregion_next; + m_axi_aruser_reg <= m_axi_aruser_next; + m_axi_arvalid_reg <= m_axi_arvalid_next; + m_axi_rready_reg <= m_axi_rready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_arready_reg <= 1'b0; + + m_axi_arvalid_reg <= 1'b0; + m_axi_rready_reg <= 1'b0; + end + end + + // output datapath logic + logic [ID_W-1:0] s_axi_rid_reg = '0; + logic [S_DATA_W-1:0] s_axi_rdata_reg = '0; + logic [1:0] s_axi_rresp_reg = 2'd0; + logic s_axi_rlast_reg = 1'b0; + logic [RUSER_W-1:0] s_axi_ruser_reg = 1'b0; + logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; + + logic [ID_W-1:0] temp_s_axi_rid_reg = '0; + logic [S_DATA_W-1:0] temp_s_axi_rdata_reg = '0; + logic [1:0] temp_s_axi_rresp_reg = 2'd0; + logic temp_s_axi_rlast_reg = 1'b0; + logic [RUSER_W-1:0] temp_s_axi_ruser_reg = 1'b0; + logic temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next; + + // datapath control + logic store_axi_r_int_to_output; + logic store_axi_r_int_to_temp; + logic store_axi_r_temp_to_output; + + assign s_axi_rd.rid = s_axi_rid_reg; + assign s_axi_rd.rdata = s_axi_rdata_reg; + assign s_axi_rd.rresp = s_axi_rresp_reg; + assign s_axi_rd.rlast = s_axi_rlast_reg; + assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0; + assign s_axi_rd.rvalid = s_axi_rvalid_reg; + + // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) + assign s_axi_rready_int_early = s_axi_rd.rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~s_axi_rvalid_int)); + + always_comb begin + // transfer sink ready state to source + s_axi_rvalid_next = s_axi_rvalid_reg; + temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg; + + store_axi_r_int_to_output = 1'b0; + store_axi_r_int_to_temp = 1'b0; + store_axi_r_temp_to_output = 1'b0; + + if (s_axi_rready_int_reg) begin + // input is ready + if (s_axi_rd.rready | ~s_axi_rvalid_reg) begin + // output is ready or currently not valid, transfer data to output + s_axi_rvalid_next = s_axi_rvalid_int; + store_axi_r_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_s_axi_rvalid_next = s_axi_rvalid_int; + store_axi_r_int_to_temp = 1'b1; + end + end else if (s_axi_rd.rready) begin + // input is not ready, but output is ready + s_axi_rvalid_next = temp_s_axi_rvalid_reg; + temp_s_axi_rvalid_next = 1'b0; + store_axi_r_temp_to_output = 1'b1; + end + end + + always_ff @(posedge clk) begin + if (rst) begin + s_axi_rvalid_reg <= 1'b0; + s_axi_rready_int_reg <= 1'b0; + temp_s_axi_rvalid_reg <= 1'b0; + end else begin + s_axi_rvalid_reg <= s_axi_rvalid_next; + s_axi_rready_int_reg <= s_axi_rready_int_early; + temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next; + end + + // datapath + if (store_axi_r_int_to_output) begin + s_axi_rid_reg <= s_axi_rid_int; + s_axi_rdata_reg <= s_axi_rdata_int; + s_axi_rresp_reg <= s_axi_rresp_int; + s_axi_rlast_reg <= s_axi_rlast_int; + s_axi_ruser_reg <= s_axi_ruser_int; + end else if (store_axi_r_temp_to_output) begin + s_axi_rid_reg <= temp_s_axi_rid_reg; + s_axi_rdata_reg <= temp_s_axi_rdata_reg; + s_axi_rresp_reg <= temp_s_axi_rresp_reg; + s_axi_rlast_reg <= temp_s_axi_rlast_reg; + s_axi_ruser_reg <= temp_s_axi_ruser_reg; + end + + if (store_axi_r_int_to_temp) begin + temp_s_axi_rid_reg <= s_axi_rid_int; + temp_s_axi_rdata_reg <= s_axi_rdata_int; + temp_s_axi_rresp_reg <= s_axi_rresp_int; + temp_s_axi_rlast_reg <= s_axi_rlast_int; + temp_s_axi_ruser_reg <= s_axi_ruser_int; + end + end + +end else begin : downsize + // output is narrower; downsize + + // output bus is wider + localparam EXPAND = M_BYTE_LANES > S_BYTE_LANES; + localparam DATA_W = EXPAND ? M_DATA_W : S_DATA_W; + localparam STRB_W = EXPAND ? M_STRB_W : S_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = EXPAND ? (M_BYTE_LANES / S_BYTE_LANES) : (S_BYTE_LANES / M_BYTE_LANES); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_DATA = 1'd1; + + logic [0:0] state_reg = STATE_IDLE, state_next; + + logic [ID_W-1:0] id_reg = '0, id_next; + logic [ADDR_W-1:0] addr_reg = '0, addr_next; + logic [DATA_W-1:0] data_reg = '0, data_next; + logic [1:0] resp_reg = '0, resp_next; + logic [RUSER_W-1:0] ruser_reg = '0, ruser_next; + logic [7:0] burst_reg = '0, burst_next; + logic [2:0] burst_size_reg = '0, burst_size_next; + logic [7:0] master_burst_reg = '0, master_burst_next; + logic [2:0] master_burst_size_reg = '0, master_burst_size_next; + + logic s_axi_arready_reg = 1'b0, s_axi_arready_next; + + logic [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next; + logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next; + logic [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next; + logic [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next; + logic [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next; + logic m_axi_arlock_reg = '0, m_axi_arlock_next; + logic [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next; + logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next; + logic [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next; + logic [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next; + logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next; + logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; + logic m_axi_rready_reg = 1'b0, m_axi_rready_next; + + // internal datapath + logic [ID_W-1:0] s_axi_rid_int; + logic [S_DATA_W-1:0] s_axi_rdata_int; + logic [1:0] s_axi_rresp_int; + logic s_axi_rlast_int; + logic [RUSER_W-1:0] s_axi_ruser_int; + logic s_axi_rvalid_int; + logic s_axi_rready_int_reg = 1'b0; + wire s_axi_rready_int_early; + + assign s_axi_rd.arready = s_axi_arready_reg; + + assign m_axi_rd.arid = '0; + assign m_axi_rd.araddr = m_axi_araddr_reg; + assign m_axi_rd.arlen = m_axi_arlen_reg; + assign m_axi_rd.arsize = m_axi_arsize_reg; + assign m_axi_rd.arburst = m_axi_arburst_reg; + assign m_axi_rd.arlock = m_axi_arlock_reg; + assign m_axi_rd.arcache = m_axi_arcache_reg; + assign m_axi_rd.arprot = m_axi_arprot_reg; + assign m_axi_rd.arqos = m_axi_arqos_reg; + assign m_axi_rd.arregion = m_axi_arregion_reg; + assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0; + assign m_axi_rd.arvalid = m_axi_arvalid_reg; + assign m_axi_rd.rready = m_axi_rready_reg; + + always_comb begin + state_next = STATE_IDLE; + + id_next = id_reg; + addr_next = addr_reg; + data_next = data_reg; + resp_next = resp_reg; + ruser_next = ruser_reg; + burst_next = burst_reg; + burst_size_next = burst_size_reg; + master_burst_next = master_burst_reg; + master_burst_size_next = master_burst_size_reg; + + s_axi_arready_next = 1'b0; + m_axi_arid_next = m_axi_arid_reg; + m_axi_araddr_next = m_axi_araddr_reg; + m_axi_arlen_next = m_axi_arlen_reg; + m_axi_arsize_next = m_axi_arsize_reg; + m_axi_arburst_next = m_axi_arburst_reg; + m_axi_arlock_next = m_axi_arlock_reg; + m_axi_arcache_next = m_axi_arcache_reg; + m_axi_arprot_next = m_axi_arprot_reg; + m_axi_arqos_next = m_axi_arqos_reg; + m_axi_arregion_next = m_axi_arregion_reg; + m_axi_aruser_next = m_axi_aruser_reg; + m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_rd.arready; + m_axi_rready_next = 1'b0; + + // master output is narrower; merge reads and possibly split burst + s_axi_rid_int = id_reg; + s_axi_rdata_int = data_reg; + s_axi_rresp_int = resp_reg; + s_axi_rlast_int = 1'b0; + s_axi_ruser_int = m_axi_rd.ruser; + s_axi_rvalid_int = 1'b0; + + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_arready_next = !m_axi_rd.arvalid; + + resp_next = 2'd0; + + if (s_axi_rd.arready && s_axi_rd.arvalid) begin + s_axi_arready_next = 1'b0; + id_next = s_axi_rd.arid; + m_axi_arid_next = s_axi_rd.arid; + m_axi_araddr_next = s_axi_rd.araddr; + addr_next = s_axi_rd.araddr; + burst_next = s_axi_rd.arlen; + burst_size_next = s_axi_rd.arsize; + if (s_axi_rd.arsize > M_BURST_SIZE) begin + // need to adjust burst size + if (s_axi_rd.arlen >> (8+M_BURST_SIZE-s_axi_rd.arsize) != 0) begin + // limit burst length to max + master_burst_next = 8'(8'd255 << 3'(s_axi_rd.arsize-M_BURST_SIZE)) | 8'((8'(~s_axi_rd.araddr) & 8'(8'hff >> (8-s_axi_rd.arsize))) >> M_BURST_SIZE); + end else begin + master_burst_next = 8'(s_axi_rd.arlen << 3'(s_axi_rd.arsize-M_BURST_SIZE)) | 8'((8'(~s_axi_rd.araddr) & 8'(8'hff >> (8-s_axi_rd.arsize))) >> M_BURST_SIZE); + end + master_burst_size_next = M_BURST_SIZE; + m_axi_arlen_next = master_burst_next; + m_axi_arsize_next = master_burst_size_next; + end else begin + // pass through narrow (enough) burst + master_burst_next = s_axi_rd.arlen; + master_burst_size_next = s_axi_rd.arsize; + m_axi_arlen_next = s_axi_rd.arlen; + m_axi_arsize_next = s_axi_rd.arsize; + end + m_axi_arburst_next = s_axi_rd.arburst; + m_axi_arlock_next = s_axi_rd.arlock; + m_axi_arcache_next = s_axi_rd.arcache; + m_axi_arprot_next = s_axi_rd.arprot; + m_axi_arqos_next = s_axi_rd.arqos; + m_axi_arregion_next = s_axi_rd.arregion; + m_axi_aruser_next = s_axi_rd.aruser; + m_axi_arvalid_next = 1'b1; + m_axi_rready_next = 1'b0; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_axi_rready_next = s_axi_rready_int_early && !m_axi_rd.arvalid; + + if (m_axi_rd.rready && m_axi_rd.rvalid) begin + data_next[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET]*SEG_DATA_W +: SEG_DATA_W] = m_axi_rd.rdata; + if (m_axi_rd.rresp != 0) begin + resp_next = m_axi_rd.rresp; + end + s_axi_rid_int = id_reg; + s_axi_rdata_int = data_next; + s_axi_rresp_int = resp_next; + s_axi_rlast_int = 1'b0; + s_axi_ruser_int = m_axi_rd.ruser; + s_axi_rvalid_int = 1'b0; + master_burst_next = master_burst_reg - 1; + addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_W{1'b1}} << master_burst_size_reg); + m_axi_araddr_next = addr_next; + if (addr_next[CL_ADDR_W'(burst_size_reg)] != addr_reg[CL_ADDR_W'(burst_size_reg)]) begin + data_next = '0; + burst_next = burst_reg - 1; + s_axi_rvalid_int = 1'b1; + end + if (master_burst_reg == 0) begin + if (burst_next >> (8+M_BURST_SIZE-burst_size_reg) != 0) begin + // limit burst length to max + master_burst_next = 8'd255; + end else begin + master_burst_next = (burst_next << (burst_size_reg-M_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> M_BURST_SIZE); + end + m_axi_arlen_next = master_burst_next; + + if (burst_reg == 0) begin + m_axi_rready_next = 1'b0; + s_axi_rlast_int = 1'b1; + s_axi_rvalid_int = 1'b1; + s_axi_arready_next = !m_axi_rd.arvalid; + state_next = STATE_IDLE; + end else begin + // start new burst + m_axi_arvalid_next = 1'b1; + m_axi_rready_next = 1'b0; + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + id_reg <= id_next; + addr_reg <= addr_next; + data_reg <= data_next; + resp_reg <= resp_next; + ruser_reg <= ruser_next; + burst_reg <= burst_next; + burst_size_reg <= burst_size_next; + master_burst_reg <= master_burst_next; + master_burst_size_reg <= master_burst_size_next; + + s_axi_arready_reg <= s_axi_arready_next; + + m_axi_arid_reg <= m_axi_arid_next; + m_axi_araddr_reg <= m_axi_araddr_next; + m_axi_arlen_reg <= m_axi_arlen_next; + m_axi_arsize_reg <= m_axi_arsize_next; + m_axi_arburst_reg <= m_axi_arburst_next; + m_axi_arlock_reg <= m_axi_arlock_next; + m_axi_arcache_reg <= m_axi_arcache_next; + m_axi_arprot_reg <= m_axi_arprot_next; + m_axi_arqos_reg <= m_axi_arqos_next; + m_axi_arregion_reg <= m_axi_arregion_next; + m_axi_aruser_reg <= m_axi_aruser_next; + m_axi_arvalid_reg <= m_axi_arvalid_next; + m_axi_rready_reg <= m_axi_rready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_arready_reg <= 1'b0; + + m_axi_arvalid_reg <= 1'b0; + m_axi_rready_reg <= 1'b0; + end + end + + // output datapath logic + logic [ID_W-1:0] s_axi_rid_reg = '0; + logic [S_DATA_W-1:0] s_axi_rdata_reg = '0; + logic [1:0] s_axi_rresp_reg = 2'd0; + logic s_axi_rlast_reg = 1'b0; + logic [RUSER_W-1:0] s_axi_ruser_reg = 1'b0; + logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; + + logic [ID_W-1:0] temp_s_axi_rid_reg = '0; + logic [S_DATA_W-1:0] temp_s_axi_rdata_reg = '0; + logic [1:0] temp_s_axi_rresp_reg = 2'd0; + logic temp_s_axi_rlast_reg = 1'b0; + logic [RUSER_W-1:0] temp_s_axi_ruser_reg = 1'b0; + logic temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next; + + // datapath control + logic store_axi_r_int_to_output; + logic store_axi_r_int_to_temp; + logic store_axi_r_temp_to_output; + + assign s_axi_rd.rid = s_axi_rid_reg; + assign s_axi_rd.rdata = s_axi_rdata_reg; + assign s_axi_rd.rresp = s_axi_rresp_reg; + assign s_axi_rd.rlast = s_axi_rlast_reg; + assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0; + assign s_axi_rd.rvalid = s_axi_rvalid_reg; + + // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) + assign s_axi_rready_int_early = s_axi_rd.rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~s_axi_rvalid_int)); + + always_comb begin + // transfer sink ready state to source + s_axi_rvalid_next = s_axi_rvalid_reg; + temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg; + + store_axi_r_int_to_output = 1'b0; + store_axi_r_int_to_temp = 1'b0; + store_axi_r_temp_to_output = 1'b0; + + if (s_axi_rready_int_reg) begin + // input is ready + if (s_axi_rd.rready | ~s_axi_rvalid_reg) begin + // output is ready or currently not valid, transfer data to output + s_axi_rvalid_next = s_axi_rvalid_int; + store_axi_r_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_s_axi_rvalid_next = s_axi_rvalid_int; + store_axi_r_int_to_temp = 1'b1; + end + end else if (s_axi_rd.rready) begin + // input is not ready, but output is ready + s_axi_rvalid_next = temp_s_axi_rvalid_reg; + temp_s_axi_rvalid_next = 1'b0; + store_axi_r_temp_to_output = 1'b1; + end + end + + always_ff @(posedge clk) begin + if (rst) begin + s_axi_rvalid_reg <= 1'b0; + s_axi_rready_int_reg <= 1'b0; + temp_s_axi_rvalid_reg <= 1'b0; + end else begin + s_axi_rvalid_reg <= s_axi_rvalid_next; + s_axi_rready_int_reg <= s_axi_rready_int_early; + temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next; + end + + // datapath + if (store_axi_r_int_to_output) begin + s_axi_rid_reg <= s_axi_rid_int; + s_axi_rdata_reg <= s_axi_rdata_int; + s_axi_rresp_reg <= s_axi_rresp_int; + s_axi_rlast_reg <= s_axi_rlast_int; + s_axi_ruser_reg <= s_axi_ruser_int; + end else if (store_axi_r_temp_to_output) begin + s_axi_rid_reg <= temp_s_axi_rid_reg; + s_axi_rdata_reg <= temp_s_axi_rdata_reg; + s_axi_rresp_reg <= temp_s_axi_rresp_reg; + s_axi_rlast_reg <= temp_s_axi_rlast_reg; + s_axi_ruser_reg <= temp_s_axi_ruser_reg; + end + + if (store_axi_r_int_to_temp) begin + temp_s_axi_rid_reg <= s_axi_rid_int; + temp_s_axi_rdata_reg <= s_axi_rdata_int; + temp_s_axi_rresp_reg <= s_axi_rresp_int; + temp_s_axi_rlast_reg <= s_axi_rlast_int; + temp_s_axi_ruser_reg <= s_axi_ruser_int; + end + end + +end + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axi_adapter_wr.sv b/src/axi/rtl/taxi_axi_adapter_wr.sv new file mode 100644 index 0000000..5f72c28 --- /dev/null +++ b/src/axi/rtl/taxi_axi_adapter_wr.sv @@ -0,0 +1,904 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 width adapter + */ +module taxi_axi_adapter_wr # +( + // When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible + parameter logic CONVERT_BURST = 1'b1, + // When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible + parameter logic CONVERT_NARROW_BURST = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interface + */ + taxi_axi_if.wr_slv s_axi_wr, + + /* + * AXI4 master interface + */ + taxi_axi_if.wr_mst m_axi_wr +); + +// extract parameters +localparam S_DATA_W = s_axi_wr.DATA_W; +localparam ADDR_W = s_axi_wr.ADDR_W; +localparam CL_ADDR_W = $clog2(ADDR_W); +localparam S_STRB_W = s_axi_wr.STRB_W; +localparam ID_W = s_axi_wr.ID_W; +localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN; +localparam AWUSER_W = s_axi_wr.AWUSER_W; +localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN; +localparam WUSER_W = s_axi_wr.WUSER_W; +localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN; +localparam BUSER_W = s_axi_wr.BUSER_W; + +localparam M_DATA_W = m_axi_wr.DATA_W; +localparam M_STRB_W = m_axi_wr.STRB_W; + +localparam S_ADDR_BIT_OFFSET = $clog2(S_STRB_W); +localparam M_ADDR_BIT_OFFSET = $clog2(M_STRB_W); +localparam S_BYTE_LANES = S_STRB_W; +localparam M_BYTE_LANES = M_STRB_W; +localparam S_BYTE_SIZE = S_DATA_W/S_BYTE_LANES; +localparam M_BYTE_SIZE = M_DATA_W/M_BYTE_LANES; +localparam logic [2:0] S_BURST_SIZE = 3'($clog2(S_STRB_W)); +localparam logic [2:0] M_BURST_SIZE = 3'($clog2(M_STRB_W)); + +// check configuration +if (S_BYTE_SIZE * S_STRB_W != S_DATA_W) + $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)"); + +if (M_BYTE_SIZE * M_STRB_W != M_DATA_W) + $fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)"); + +if (S_BYTE_SIZE != M_BYTE_SIZE) + $fatal(0, "Error: byte size mismatch (instance %m)"); + +if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES) + $fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)"); + +if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES) + $fatal(0, "Error: AXI master interface byte lane count must be even power of two (instance %m)"); + +if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass + // same width; bypass + + assign m_axi_wr.awid = s_axi_wr.awid; + assign m_axi_wr.awaddr = s_axi_wr.awaddr; + assign m_axi_wr.awlen = s_axi_wr.awlen; + assign m_axi_wr.awsize = s_axi_wr.awsize; + assign m_axi_wr.awburst = s_axi_wr.awburst; + assign m_axi_wr.awlock = s_axi_wr.awlock; + assign m_axi_wr.awcache = s_axi_wr.awcache; + assign m_axi_wr.awprot = s_axi_wr.awprot; + assign m_axi_wr.awqos = s_axi_wr.awqos; + assign m_axi_wr.awregion = s_axi_wr.awregion; + assign m_axi_wr.awuser = AWUSER_EN ? s_axi_wr.awuser : '0; + assign m_axi_wr.awvalid = s_axi_wr.awvalid; + assign s_axi_wr.awready = m_axi_wr.awready; + + assign m_axi_wr.wdata = s_axi_wr.wdata; + assign m_axi_wr.wstrb = s_axi_wr.wstrb; + assign m_axi_wr.wlast = s_axi_wr.wlast; + assign m_axi_wr.wuser = WUSER_EN ? s_axi_wr.wuser : '0; + assign m_axi_wr.wvalid = s_axi_wr.wvalid; + assign s_axi_wr.wready = m_axi_wr.wready; + + assign s_axi_wr.bid = m_axi_wr.bid; + assign s_axi_wr.bresp = m_axi_wr.bresp; + assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0; + assign s_axi_wr.bvalid = m_axi_wr.bvalid; + assign m_axi_wr.bready = s_axi_wr.bready; + +end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize + // output is wider; upsize + + // output bus is wider + localparam EXPAND = M_BYTE_LANES > S_BYTE_LANES; + localparam DATA_W = EXPAND ? M_DATA_W : S_DATA_W; + localparam STRB_W = EXPAND ? M_STRB_W : S_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = EXPAND ? (M_BYTE_LANES / S_BYTE_LANES) : (S_BYTE_LANES / M_BYTE_LANES); + localparam CL_SEG_COUNT = $clog2(SEG_COUNT); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [1:0] + STATE_IDLE = 2'd0, + STATE_DATA = 2'd1, + STATE_DATA_2 = 2'd2, + STATE_RESP = 2'd3; + + logic [1:0] state_reg = STATE_IDLE, state_next; + + logic [ID_W-1:0] id_reg = '0, id_next; + logic [ADDR_W-1:0] addr_reg = '0, addr_next; + logic [DATA_W-1:0] data_reg = '0, data_next; + logic [STRB_W-1:0] strb_reg = '0, strb_next; + logic [WUSER_W-1:0] wuser_reg = '0, wuser_next; + logic [7:0] burst_reg = '0, burst_next; + logic [2:0] burst_size_reg = '0, burst_size_next; + logic [2:0] master_burst_size_reg = '0, master_burst_size_next; + logic burst_active_reg = 1'b0, burst_active_next; + logic first_transfer_reg = 1'b0, first_transfer_next; + + logic s_axi_awready_reg = 1'b0, s_axi_awready_next; + logic s_axi_wready_reg = 1'b0, s_axi_wready_next; + logic [ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next; + logic [1:0] s_axi_bresp_reg = '0, s_axi_bresp_next; + logic [BUSER_W-1:0] s_axi_buser_reg = '0, s_axi_buser_next; + logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; + + logic [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next; + logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next; + logic [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next; + logic [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next; + logic [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next; + logic m_axi_awlock_reg = '0, m_axi_awlock_next; + logic [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next; + logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next; + logic [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next; + logic [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next; + logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next; + logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; + logic m_axi_bready_reg = 1'b0, m_axi_bready_next; + + // internal datapath + logic [M_DATA_W-1:0] m_axi_wdata_int; + logic [M_STRB_W-1:0] m_axi_wstrb_int; + logic m_axi_wlast_int; + logic [WUSER_W-1:0] m_axi_wuser_int; + logic m_axi_wvalid_int; + logic m_axi_wready_int_reg = 1'b0; + wire m_axi_wready_int_early; + + assign s_axi_wr.awready = s_axi_awready_reg; + assign s_axi_wr.wready = s_axi_wready_reg; + assign s_axi_wr.bid = s_axi_bid_reg; + assign s_axi_wr.bresp = s_axi_bresp_reg; + assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0; + assign s_axi_wr.bvalid = s_axi_bvalid_reg; + + assign m_axi_wr.awid = '0; + assign m_axi_wr.awaddr = m_axi_awaddr_reg; + assign m_axi_wr.awlen = m_axi_awlen_reg; + assign m_axi_wr.awsize = m_axi_awsize_reg; + assign m_axi_wr.awburst = m_axi_awburst_reg; + assign m_axi_wr.awlock = m_axi_awlock_reg; + assign m_axi_wr.awcache = m_axi_awcache_reg; + assign m_axi_wr.awprot = m_axi_awprot_reg; + assign m_axi_wr.awqos = m_axi_awqos_reg; + assign m_axi_wr.awregion = m_axi_awregion_reg; + assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0; + assign m_axi_wr.awvalid = m_axi_awvalid_reg; + assign m_axi_wr.bready = m_axi_bready_reg; + + always_comb begin + state_next = STATE_IDLE; + + id_next = id_reg; + addr_next = addr_reg; + data_next = data_reg; + strb_next = strb_reg; + wuser_next = wuser_reg; + burst_next = burst_reg; + burst_size_next = burst_size_reg; + master_burst_size_next = master_burst_size_reg; + burst_active_next = burst_active_reg; + first_transfer_next = first_transfer_reg; + + s_axi_awready_next = 1'b0; + s_axi_wready_next = 1'b0; + s_axi_bid_next = s_axi_bid_reg; + s_axi_bresp_next = s_axi_bresp_reg; + s_axi_buser_next = s_axi_buser_reg; + s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready; + m_axi_awid_next = m_axi_awid_reg; + m_axi_awaddr_next = m_axi_awaddr_reg; + m_axi_awlen_next = m_axi_awlen_reg; + m_axi_awsize_next = m_axi_awsize_reg; + m_axi_awburst_next = m_axi_awburst_reg; + m_axi_awlock_next = m_axi_awlock_reg; + m_axi_awcache_next = m_axi_awcache_reg; + m_axi_awprot_next = m_axi_awprot_reg; + m_axi_awqos_next = m_axi_awqos_reg; + m_axi_awregion_next = m_axi_awregion_reg; + m_axi_awuser_next = m_axi_awuser_reg; + m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready; + m_axi_bready_next = 1'b0; + + m_axi_wdata_int = {(M_BYTE_LANES/S_BYTE_LANES){s_axi_wr.wdata}}; + m_axi_wstrb_int = 0; + m_axi_wstrb_int[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_STRB_W +: S_STRB_W] = s_axi_wr.wstrb; + m_axi_wlast_int = s_axi_wr.wlast; + m_axi_wuser_int = s_axi_wr.wuser; + m_axi_wvalid_int = 1'b0; + + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_awready_next = !m_axi_wr.awvalid; + + strb_next = '0; + + if (s_axi_wr.awready && s_axi_wr.awvalid) begin + s_axi_awready_next = 1'b0; + id_next = s_axi_wr.awid; + m_axi_awid_next = s_axi_wr.awid; + m_axi_awaddr_next = s_axi_wr.awaddr; + addr_next = s_axi_wr.awaddr; + burst_next = s_axi_wr.awlen; + burst_size_next = s_axi_wr.awsize; + if (CONVERT_BURST && s_axi_wr.awcache[1] && (CONVERT_NARROW_BURST || s_axi_wr.awsize == S_BURST_SIZE)) begin + // merge writes + // require CONVERT_BURST and awcache[1] set + master_burst_size_next = M_BURST_SIZE; + if (CONVERT_NARROW_BURST) begin + m_axi_awlen_next = 8'((({8'd0, s_axi_wr.awlen} << s_axi_wr.awsize) + 16'(s_axi_wr.awaddr[M_ADDR_BIT_OFFSET-1:0])) >> M_BURST_SIZE); + end else begin + m_axi_awlen_next = (s_axi_wr.awlen + 8'(s_axi_wr.awaddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET])) >> CL_SEG_COUNT; + end + m_axi_awsize_next = M_BURST_SIZE; + state_next = STATE_DATA_2; + end else begin + // output narrow burst + master_burst_size_next = s_axi_wr.awsize; + m_axi_awlen_next = s_axi_wr.awlen; + m_axi_awsize_next = s_axi_wr.awsize; + state_next = STATE_DATA; + end + m_axi_awburst_next = s_axi_wr.awburst; + m_axi_awlock_next = s_axi_wr.awlock; + m_axi_awcache_next = s_axi_wr.awcache; + m_axi_awprot_next = s_axi_wr.awprot; + m_axi_awqos_next = s_axi_wr.awqos; + m_axi_awregion_next = s_axi_wr.awregion; + m_axi_awuser_next = s_axi_wr.awuser; + m_axi_awvalid_next = 1'b1; + s_axi_wready_next = m_axi_wready_int_early; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + // data state; transfer write data + s_axi_wready_next = m_axi_wready_int_early; + + if (s_axi_wr.wready && s_axi_wr.wvalid) begin + m_axi_wdata_int = {(M_BYTE_LANES/S_BYTE_LANES){s_axi_wr.wdata}}; + m_axi_wstrb_int = 0; + m_axi_wstrb_int[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET] * S_STRB_W +: S_STRB_W] = s_axi_wr.wstrb; + m_axi_wlast_int = s_axi_wr.wlast; + m_axi_wuser_int = s_axi_wr.wuser; + m_axi_wvalid_int = 1'b1; + addr_next = addr_reg + (1 << burst_size_reg); + if (s_axi_wr.wlast) begin + s_axi_wready_next = 1'b0; + m_axi_bready_next = !s_axi_wr.bvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + STATE_DATA_2: begin + s_axi_wready_next = m_axi_wready_int_early; + + if (s_axi_wr.wready && s_axi_wr.wvalid) begin + if (CONVERT_NARROW_BURST) begin + for (integer i = 0; i < S_BYTE_LANES; i = i + 1) begin + if (s_axi_wr.wstrb[i]) begin + data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEG_DATA_W+i*M_BYTE_SIZE +: M_BYTE_SIZE] = s_axi_wr.wdata[i*M_BYTE_SIZE +: M_BYTE_SIZE]; + strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEG_STRB_W+i] = 1'b1; + end + end + end else begin + data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEG_DATA_W +: SEG_DATA_W] = s_axi_wr.wdata; + strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*SEG_STRB_W +: SEG_STRB_W] = s_axi_wr.wstrb; + end + m_axi_wdata_int = data_next; + m_axi_wstrb_int = strb_next; + m_axi_wlast_int = s_axi_wr.wlast; + m_axi_wuser_int = s_axi_wr.wuser; + burst_next = burst_reg - 1; + addr_next = addr_reg + (1 << burst_size_reg); + if (addr_next[CL_ADDR_W'(master_burst_size_reg)] != addr_reg[CL_ADDR_W'(master_burst_size_reg)]) begin + strb_next = '0; + m_axi_wvalid_int = 1'b1; + end + if (burst_reg == 0) begin + m_axi_wvalid_int = 1'b1; + s_axi_wready_next = 1'b0; + m_axi_bready_next = !s_axi_wr.bvalid; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA_2; + end + end else begin + state_next = STATE_DATA_2; + end + end + STATE_RESP: begin + // resp state; transfer write response + m_axi_bready_next = !s_axi_wr.bvalid; + + if (m_axi_wr.bready && m_axi_wr.bvalid) begin + m_axi_bready_next = 1'b0; + s_axi_bid_next = id_reg; + s_axi_bresp_next = m_axi_wr.bresp; + s_axi_buser_next = m_axi_wr.buser; + s_axi_bvalid_next = 1'b1; + s_axi_awready_next = !m_axi_wr.awvalid; + state_next = STATE_IDLE; + end else begin + state_next = STATE_RESP; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + id_reg <= id_next; + addr_reg <= addr_next; + data_reg <= data_next; + strb_reg <= strb_next; + wuser_reg <= wuser_next; + burst_reg <= burst_next; + burst_size_reg <= burst_size_next; + master_burst_size_reg <= master_burst_size_next; + burst_active_reg <= burst_active_next; + first_transfer_reg <= first_transfer_next; + + s_axi_awready_reg <= s_axi_awready_next; + s_axi_wready_reg <= s_axi_wready_next; + s_axi_bid_reg <= s_axi_bid_next; + s_axi_bresp_reg <= s_axi_bresp_next; + s_axi_buser_reg <= s_axi_buser_next; + s_axi_bvalid_reg <= s_axi_bvalid_next; + + m_axi_awid_reg <= m_axi_awid_next; + m_axi_awaddr_reg <= m_axi_awaddr_next; + m_axi_awlen_reg <= m_axi_awlen_next; + m_axi_awsize_reg <= m_axi_awsize_next; + m_axi_awburst_reg <= m_axi_awburst_next; + m_axi_awlock_reg <= m_axi_awlock_next; + m_axi_awcache_reg <= m_axi_awcache_next; + m_axi_awprot_reg <= m_axi_awprot_next; + m_axi_awqos_reg <= m_axi_awqos_next; + m_axi_awregion_reg <= m_axi_awregion_next; + m_axi_awuser_reg <= m_axi_awuser_next; + m_axi_awvalid_reg <= m_axi_awvalid_next; + m_axi_bready_reg <= m_axi_bready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_awready_reg <= 1'b0; + s_axi_wready_reg <= 1'b0; + s_axi_bvalid_reg <= 1'b0; + + m_axi_awvalid_reg <= 1'b0; + m_axi_bready_reg <= 1'b0; + end + end + + // output datapath logic + logic [M_DATA_W-1:0] m_axi_wdata_reg = '0; + logic [M_STRB_W-1:0] m_axi_wstrb_reg = '0; + logic m_axi_wlast_reg = 1'b0; + logic [WUSER_W-1:0] m_axi_wuser_reg = 1'b0; + logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; + + logic [M_DATA_W-1:0] temp_m_axi_wdata_reg = '0; + logic [M_STRB_W-1:0] temp_m_axi_wstrb_reg = '0; + logic temp_m_axi_wlast_reg = 1'b0; + logic [WUSER_W-1:0] temp_m_axi_wuser_reg = 1'b0; + logic temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next; + + // datapath control + logic store_axi_w_int_to_output; + logic store_axi_w_int_to_temp; + logic store_axi_w_temp_to_output; + + assign m_axi_wr.wdata = m_axi_wdata_reg; + assign m_axi_wr.wstrb = m_axi_wstrb_reg; + assign m_axi_wr.wlast = m_axi_wlast_reg; + assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0; + assign m_axi_wr.wvalid = m_axi_wvalid_reg; + + // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) + assign m_axi_wready_int_early = m_axi_wr.wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~m_axi_wvalid_int)); + + always_comb begin + // transfer sink ready state to source + m_axi_wvalid_next = m_axi_wvalid_reg; + temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg; + + store_axi_w_int_to_output = 1'b0; + store_axi_w_int_to_temp = 1'b0; + store_axi_w_temp_to_output = 1'b0; + + if (m_axi_wready_int_reg) begin + // input is ready + if (m_axi_wr.wready | ~m_axi_wvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axi_wvalid_next = m_axi_wvalid_int; + store_axi_w_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axi_wvalid_next = m_axi_wvalid_int; + store_axi_w_int_to_temp = 1'b1; + end + end else if (m_axi_wr.wready) begin + // input is not ready, but output is ready + m_axi_wvalid_next = temp_m_axi_wvalid_reg; + temp_m_axi_wvalid_next = 1'b0; + store_axi_w_temp_to_output = 1'b1; + end + end + + always_ff @(posedge clk) begin + if (rst) begin + m_axi_wvalid_reg <= 1'b0; + m_axi_wready_int_reg <= 1'b0; + temp_m_axi_wvalid_reg <= 1'b0; + end else begin + m_axi_wvalid_reg <= m_axi_wvalid_next; + m_axi_wready_int_reg <= m_axi_wready_int_early; + temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next; + end + + // datapath + if (store_axi_w_int_to_output) begin + m_axi_wdata_reg <= m_axi_wdata_int; + m_axi_wstrb_reg <= m_axi_wstrb_int; + m_axi_wlast_reg <= m_axi_wlast_int; + m_axi_wuser_reg <= m_axi_wuser_int; + end else if (store_axi_w_temp_to_output) begin + m_axi_wdata_reg <= temp_m_axi_wdata_reg; + m_axi_wstrb_reg <= temp_m_axi_wstrb_reg; + m_axi_wlast_reg <= temp_m_axi_wlast_reg; + m_axi_wuser_reg <= temp_m_axi_wuser_reg; + end + + if (store_axi_w_int_to_temp) begin + temp_m_axi_wdata_reg <= m_axi_wdata_int; + temp_m_axi_wstrb_reg <= m_axi_wstrb_int; + temp_m_axi_wlast_reg <= m_axi_wlast_int; + temp_m_axi_wuser_reg <= m_axi_wuser_int; + end + end + +end else begin : downsize + // output is narrower; downsize + + // output bus is wider + localparam EXPAND = M_BYTE_LANES > S_BYTE_LANES; + localparam DATA_W = EXPAND ? M_DATA_W : S_DATA_W; + localparam STRB_W = EXPAND ? M_STRB_W : S_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = EXPAND ? (M_BYTE_LANES / S_BYTE_LANES) : (S_BYTE_LANES / M_BYTE_LANES); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [1:0] + STATE_IDLE = 2'd0, + STATE_DATA = 2'd1, + STATE_DATA_2 = 2'd2, + STATE_RESP = 2'd3; + + logic [1:0] state_reg = STATE_IDLE, state_next; + + logic [ID_W-1:0] id_reg = '0, id_next; + logic [ADDR_W-1:0] addr_reg = '0, addr_next; + logic [DATA_W-1:0] data_reg = '0, data_next; + logic [STRB_W-1:0] strb_reg = '0, strb_next; + logic [WUSER_W-1:0] wuser_reg = '0, wuser_next; + logic [7:0] burst_reg = '0, burst_next; + logic [2:0] burst_size_reg = '0, burst_size_next; + logic [7:0] master_burst_reg = '0, master_burst_next; + logic [2:0] master_burst_size_reg = '0, master_burst_size_next; + logic burst_active_reg = 1'b0, burst_active_next; + logic first_transfer_reg = 1'b0, first_transfer_next; + + logic s_axi_awready_reg = 1'b0, s_axi_awready_next; + logic s_axi_wready_reg = 1'b0, s_axi_wready_next; + logic [ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next; + logic [1:0] s_axi_bresp_reg = '0, s_axi_bresp_next; + logic [BUSER_W-1:0] s_axi_buser_reg = '0, s_axi_buser_next; + logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; + + logic [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next; + logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next; + logic [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next; + logic [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next; + logic [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next; + logic m_axi_awlock_reg = '0, m_axi_awlock_next; + logic [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next; + logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next; + logic [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next; + logic [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next; + logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next; + logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; + logic m_axi_bready_reg = 1'b0, m_axi_bready_next; + + // internal datapath + logic [M_DATA_W-1:0] m_axi_wdata_int; + logic [M_STRB_W-1:0] m_axi_wstrb_int; + logic m_axi_wlast_int; + logic [WUSER_W-1:0] m_axi_wuser_int; + logic m_axi_wvalid_int; + logic m_axi_wready_int_reg = 1'b0; + wire m_axi_wready_int_early; + + assign s_axi_wr.awready = s_axi_awready_reg; + assign s_axi_wr.wready = s_axi_wready_reg; + assign s_axi_wr.bid = s_axi_bid_reg; + assign s_axi_wr.bresp = s_axi_bresp_reg; + assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0; + assign s_axi_wr.bvalid = s_axi_bvalid_reg; + + assign m_axi_wr.awid = '0; + assign m_axi_wr.awaddr = m_axi_awaddr_reg; + assign m_axi_wr.awlen = m_axi_awlen_reg; + assign m_axi_wr.awsize = m_axi_awsize_reg; + assign m_axi_wr.awburst = m_axi_awburst_reg; + assign m_axi_wr.awlock = m_axi_awlock_reg; + assign m_axi_wr.awcache = m_axi_awcache_reg; + assign m_axi_wr.awprot = m_axi_awprot_reg; + assign m_axi_wr.awqos = m_axi_awqos_reg; + assign m_axi_wr.awregion = m_axi_awregion_reg; + assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0; + assign m_axi_wr.awvalid = m_axi_awvalid_reg; + assign m_axi_wr.bready = m_axi_bready_reg; + + always_comb begin + state_next = STATE_IDLE; + + id_next = id_reg; + addr_next = addr_reg; + data_next = data_reg; + strb_next = strb_reg; + wuser_next = wuser_reg; + burst_next = burst_reg; + burst_size_next = burst_size_reg; + master_burst_next = master_burst_reg; + master_burst_size_next = master_burst_size_reg; + burst_active_next = burst_active_reg; + first_transfer_next = first_transfer_reg; + + s_axi_awready_next = 1'b0; + s_axi_wready_next = 1'b0; + s_axi_bid_next = s_axi_bid_reg; + s_axi_bresp_next = s_axi_bresp_reg; + s_axi_buser_next = s_axi_buser_reg; + s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready; + m_axi_awid_next = m_axi_awid_reg; + m_axi_awaddr_next = m_axi_awaddr_reg; + m_axi_awlen_next = m_axi_awlen_reg; + m_axi_awsize_next = m_axi_awsize_reg; + m_axi_awburst_next = m_axi_awburst_reg; + m_axi_awlock_next = m_axi_awlock_reg; + m_axi_awcache_next = m_axi_awcache_reg; + m_axi_awprot_next = m_axi_awprot_reg; + m_axi_awqos_next = m_axi_awqos_reg; + m_axi_awregion_next = m_axi_awregion_reg; + m_axi_awuser_next = m_axi_awuser_reg; + m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready; + m_axi_bready_next = 1'b0; + + m_axi_wdata_int = data_reg[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_W +: M_DATA_W]; + m_axi_wstrb_int = strb_reg[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_W +: M_STRB_W]; + m_axi_wlast_int = 1'b0; + m_axi_wuser_int = wuser_reg; + m_axi_wvalid_int = 1'b0; + + case (state_reg) + STATE_IDLE: begin + // idle state; wait for new burst + s_axi_awready_next = !m_axi_wr.awvalid; + + first_transfer_next = 1'b1; + + if (s_axi_wr.awready && s_axi_wr.awvalid) begin + s_axi_awready_next = 1'b0; + id_next = s_axi_wr.awid; + m_axi_awid_next = s_axi_wr.awid; + m_axi_awaddr_next = s_axi_wr.awaddr; + addr_next = s_axi_wr.awaddr; + burst_next = s_axi_wr.awlen; + burst_size_next = s_axi_wr.awsize; + burst_active_next = 1'b1; + if (s_axi_wr.awsize > M_BURST_SIZE) begin + // need to adjust burst size + if (s_axi_wr.awlen >> (8+M_BURST_SIZE-s_axi_wr.awsize) != 0) begin + // limit burst length to max + master_burst_next = 8'(32'hff << 3'(s_axi_wr.awsize-M_BURST_SIZE)) | 8'((8'(~s_axi_wr.awaddr) & 8'(8'hff >> (8-s_axi_wr.awsize))) >> M_BURST_SIZE); + end else begin + master_burst_next = 8'(s_axi_wr.awlen << 3'(s_axi_wr.awsize-M_BURST_SIZE)) | 8'((8'(~s_axi_wr.awaddr) & 8'(8'hff >> (8-s_axi_wr.awsize))) >> M_BURST_SIZE); + end + master_burst_size_next = M_BURST_SIZE; + m_axi_awlen_next = master_burst_next; + m_axi_awsize_next = master_burst_size_next; + end else begin + // pass through narrow (enough) burst + master_burst_next = s_axi_wr.awlen; + master_burst_size_next = s_axi_wr.awsize; + m_axi_awlen_next = s_axi_wr.awlen; + m_axi_awsize_next = s_axi_wr.awsize; + end + m_axi_awburst_next = s_axi_wr.awburst; + m_axi_awlock_next = s_axi_wr.awlock; + m_axi_awcache_next = s_axi_wr.awcache; + m_axi_awprot_next = s_axi_wr.awprot; + m_axi_awqos_next = s_axi_wr.awqos; + m_axi_awregion_next = s_axi_wr.awregion; + m_axi_awuser_next = s_axi_wr.awuser; + m_axi_awvalid_next = 1'b1; + s_axi_wready_next = m_axi_wready_int_early; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + s_axi_wready_next = m_axi_wready_int_early; + + if (s_axi_wr.wready && s_axi_wr.wvalid) begin + data_next = s_axi_wr.wdata; + strb_next = s_axi_wr.wstrb; + wuser_next = s_axi_wr.wuser; + m_axi_wdata_int = s_axi_wr.wdata[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_W +: M_DATA_W]; + m_axi_wstrb_int = s_axi_wr.wstrb[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_W +: M_STRB_W]; + m_axi_wlast_int = 1'b0; + m_axi_wuser_int = s_axi_wr.wuser; + m_axi_wvalid_int = 1'b1; + burst_next = burst_reg - 1; + burst_active_next = burst_reg != 0; + master_burst_next = master_burst_reg - 1; + addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_W{1'b1}} << master_burst_size_reg); + if (master_burst_reg == 0) begin + s_axi_wready_next = 1'b0; + m_axi_bready_next = !s_axi_wr.bvalid && !s_axi_wr.awvalid; + m_axi_wlast_int = 1'b1; + state_next = STATE_RESP; + end else if (addr_next[CL_ADDR_W'(burst_size_reg)] != addr_reg[CL_ADDR_W'(burst_size_reg)]) begin + state_next = STATE_DATA; + end else begin + s_axi_wready_next = 1'b0; + state_next = STATE_DATA_2; + end + end else begin + state_next = STATE_DATA; + end + end + STATE_DATA_2: begin + s_axi_wready_next = 1'b0; + + if (m_axi_wready_int_reg) begin + m_axi_wdata_int = data_reg[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_DATA_W +: M_DATA_W]; + m_axi_wstrb_int = strb_reg[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET] * M_STRB_W +: M_STRB_W]; + m_axi_wlast_int = 1'b0; + m_axi_wuser_int = wuser_reg; + m_axi_wvalid_int = 1'b1; + master_burst_next = master_burst_reg - 1; + addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_W{1'b1}} << master_burst_size_reg); + if (master_burst_reg == 0) begin + // burst on master interface finished; transfer response + s_axi_wready_next = 1'b0; + m_axi_bready_next = !s_axi_wr.bvalid && !m_axi_wr.awvalid; + m_axi_wlast_int = 1'b1; + state_next = STATE_RESP; + end else if (addr_next[CL_ADDR_W'(burst_size_reg)] != addr_reg[CL_ADDR_W'(burst_size_reg)]) begin + state_next = STATE_DATA; + end else begin + s_axi_wready_next = 1'b0; + state_next = STATE_DATA_2; + end + end else begin + state_next = STATE_DATA_2; + end + end + STATE_RESP: begin + // resp state; transfer write response + m_axi_bready_next = !s_axi.bvalid && !m_axi.awvalid; + + if (m_axi.bready && m_axi.bvalid) begin + first_transfer_next = 1'b0; + m_axi_bready_next = 1'b0; + s_axi_bid_next = id_reg; + if (first_transfer_reg || m_axi.bresp != 0) begin + s_axi_bresp_next = m_axi.bresp; + end + + if (burst_reg >> (8+M_BURST_SIZE-burst_size_reg) != 0) begin + // limit burst length to max + master_burst_next = 8'd255; + end else begin + master_burst_next = (burst_reg << (burst_size_reg-M_BURST_SIZE)) | (8'hff >> (8-burst_size_reg) >> M_BURST_SIZE); + end + master_burst_size_next = M_BURST_SIZE; + m_axi_awaddr_next = addr_reg; + m_axi_awlen_next = master_burst_next; + m_axi_awsize_next = master_burst_size_next; + if (burst_active_reg) begin + // burst on slave interface still active; start new burst + m_axi_awvalid_next = 1'b1; + state_next = STATE_DATA; + end else begin + // burst on slave interface finished; return to idle + s_axi_bvalid_next = 1'b1; + s_axi_awready_next = !m_axi.awvalid; + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_RESP; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + id_reg <= id_next; + addr_reg <= addr_next; + data_reg <= data_next; + strb_reg <= strb_next; + wuser_reg <= wuser_next; + burst_reg <= burst_next; + burst_size_reg <= burst_size_next; + master_burst_reg <= master_burst_next; + master_burst_size_reg <= master_burst_size_next; + burst_active_reg <= burst_active_next; + first_transfer_reg <= first_transfer_next; + + s_axi_awready_reg <= s_axi_awready_next; + s_axi_wready_reg <= s_axi_wready_next; + s_axi_bid_reg <= s_axi_bid_next; + s_axi_bresp_reg <= s_axi_bresp_next; + s_axi_buser_reg <= s_axi_buser_next; + s_axi_bvalid_reg <= s_axi_bvalid_next; + + m_axi_awid_reg <= m_axi_awid_next; + m_axi_awaddr_reg <= m_axi_awaddr_next; + m_axi_awlen_reg <= m_axi_awlen_next; + m_axi_awsize_reg <= m_axi_awsize_next; + m_axi_awburst_reg <= m_axi_awburst_next; + m_axi_awlock_reg <= m_axi_awlock_next; + m_axi_awcache_reg <= m_axi_awcache_next; + m_axi_awprot_reg <= m_axi_awprot_next; + m_axi_awqos_reg <= m_axi_awqos_next; + m_axi_awregion_reg <= m_axi_awregion_next; + m_axi_awuser_reg <= m_axi_awuser_next; + m_axi_awvalid_reg <= m_axi_awvalid_next; + m_axi_bready_reg <= m_axi_bready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axi_awready_reg <= 1'b0; + s_axi_wready_reg <= 1'b0; + s_axi_bvalid_reg <= 1'b0; + + m_axi_awvalid_reg <= 1'b0; + m_axi_bready_reg <= 1'b0; + end + end + + // output datapath logic + logic [M_DATA_W-1:0] m_axi_wdata_reg = '0; + logic [M_STRB_W-1:0] m_axi_wstrb_reg = '0; + logic m_axi_wlast_reg = 1'b0; + logic [WUSER_W-1:0] m_axi_wuser_reg = 1'b0; + logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; + + logic [M_DATA_W-1:0] temp_m_axi_wdata_reg = '0; + logic [M_STRB_W-1:0] temp_m_axi_wstrb_reg = '0; + logic temp_m_axi_wlast_reg = 1'b0; + logic [WUSER_W-1:0] temp_m_axi_wuser_reg = 1'b0; + logic temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next; + + // datapath control + logic store_axi_w_int_to_output; + logic store_axi_w_int_to_temp; + logic store_axi_w_temp_to_output; + + assign m_axi_wr.wdata = m_axi_wdata_reg; + assign m_axi_wr.wstrb = m_axi_wstrb_reg; + assign m_axi_wr.wlast = m_axi_wlast_reg; + assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0; + assign m_axi_wr.wvalid = m_axi_wvalid_reg; + + // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) + assign m_axi_wready_int_early = m_axi_wr.wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~m_axi_wvalid_int)); + + always_comb begin + // transfer sink ready state to source + m_axi_wvalid_next = m_axi_wvalid_reg; + temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg; + + store_axi_w_int_to_output = 1'b0; + store_axi_w_int_to_temp = 1'b0; + store_axi_w_temp_to_output = 1'b0; + + if (m_axi_wready_int_reg) begin + // input is ready + if (m_axi_wr.wready | ~m_axi_wvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axi_wvalid_next = m_axi_wvalid_int; + store_axi_w_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axi_wvalid_next = m_axi_wvalid_int; + store_axi_w_int_to_temp = 1'b1; + end + end else if (m_axi_wr.wready) begin + // input is not ready, but output is ready + m_axi_wvalid_next = temp_m_axi_wvalid_reg; + temp_m_axi_wvalid_next = 1'b0; + store_axi_w_temp_to_output = 1'b1; + end + end + + always_ff @(posedge clk) begin + if (rst) begin + m_axi_wvalid_reg <= 1'b0; + m_axi_wready_int_reg <= 1'b0; + temp_m_axi_wvalid_reg <= 1'b0; + end else begin + m_axi_wvalid_reg <= m_axi_wvalid_next; + m_axi_wready_int_reg <= m_axi_wready_int_early; + temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next; + end + + // datapath + if (store_axi_w_int_to_output) begin + m_axi_wdata_reg <= m_axi_wdata_int; + m_axi_wstrb_reg <= m_axi_wstrb_int; + m_axi_wlast_reg <= m_axi_wlast_int; + m_axi_wuser_reg <= m_axi_wuser_int; + end else if (store_axi_w_temp_to_output) begin + m_axi_wdata_reg <= temp_m_axi_wdata_reg; + m_axi_wstrb_reg <= temp_m_axi_wstrb_reg; + m_axi_wlast_reg <= temp_m_axi_wlast_reg; + m_axi_wuser_reg <= temp_m_axi_wuser_reg; + end + + if (store_axi_w_int_to_temp) begin + temp_m_axi_wdata_reg <= m_axi_wdata_int; + temp_m_axi_wstrb_reg <= m_axi_wstrb_int; + temp_m_axi_wlast_reg <= m_axi_wlast_int; + temp_m_axi_wuser_reg <= m_axi_wuser_int; + end + end + +end + +endmodule + +`resetall diff --git a/src/axi/tb/taxi_axi_adapter/Makefile b/src/axi/tb/taxi_axi_adapter/Makefile new file mode 100644 index 0000000..c818852 --- /dev/null +++ b/src/axi/tb/taxi_axi_adapter/Makefile @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_axi_adapter +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_ADDR_W := 32 +export PARAM_S_DATA_W := 32 +export PARAM_S_STRB_W := $(shell expr $(PARAM_S_DATA_W) / 8 ) +export PARAM_S_ID_W := 8 +export PARAM_M_DATA_W := 32 +export PARAM_M_STRB_W := $(shell expr $(PARAM_M_DATA_W) / 8 ) +export PARAM_M_ID_W := 8 +export PARAM_AWUSER_EN := 0 +export PARAM_AWUSER_W := 1 +export PARAM_WUSER_EN := 0 +export PARAM_WUSER_W := 1 +export PARAM_BUSER_EN := 0 +export PARAM_BUSER_W := 1 +export PARAM_ARUSER_EN := 0 +export PARAM_ARUSER_W := 1 +export PARAM_RUSER_EN := 0 +export PARAM_RUSER_W := 1 +export PARAM_CONVERT_BURST := 1 +export PARAM_CONVERT_NARROW_BURST := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.py b/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.py new file mode 100644 index 0000000..59c0bde --- /dev/null +++ b/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.py @@ -0,0 +1,263 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiBus, AxiMaster, AxiRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst) + self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16) + + def set_idle_generator(self, generator=None): + if generator: + self.axi_master.write_if.aw_channel.set_pause_generator(generator()) + self.axi_master.write_if.w_channel.set_pause_generator(generator()) + self.axi_master.read_if.ar_channel.set_pause_generator(generator()) + self.axi_ram.write_if.b_channel.set_pause_generator(generator()) + self.axi_ram.read_if.r_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axi_master.write_if.b_channel.set_pause_generator(generator()) + self.axi_master.read_if.r_channel.set_pause_generator(generator()) + self.axi_ram.write_if.aw_channel.set_pause_generator(generator()) + self.axi_ram.write_if.w_channel.set_pause_generator(generator()) + self.axi_ram.read_if.ar_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None): + + tb = TB(dut) + + byte_lanes = tb.axi_master.write_if.byte_lanes + max_burst_size = tb.axi_master.write_if.max_burst_size + + if size is None: + size = max_burst_size + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)): + tb.log.info("length %d, offset %d, size %d", length, offset, size) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram.write(addr-128, b'\xaa'*(length+256)) + + await tb.axi_master.write(addr, test_data, size=size) + + tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.axi_ram.read(addr, length) == test_data + assert tb.axi_ram.read(addr-1, 1) == b'\xaa' + assert tb.axi_ram.read(addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None): + + tb = TB(dut) + + byte_lanes = tb.axi_master.write_if.byte_lanes + max_burst_size = tb.axi_master.write_if.max_burst_size + + if size is None: + size = max_burst_size + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes, byte_lanes*2))+[4096-byte_lanes]: + tb.log.info("length %d, offset %d, size %d", length, offset, size) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram.write(addr, test_data) + + data = await tb.axi_master.read(addr, length, size=size) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(512, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if cocotb.SIM_NAME: + + data_width = len(cocotb.top.s_axi.wdata) + byte_lanes = data_width // 8 + max_burst_size = (byte_lanes-1).bit_length() + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.add_option("size", [None]+list(range(max_burst_size))) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("m_data_w", [8, 16, 32]) +@pytest.mark.parametrize("s_data_w", [8, 16, 32]) +def test_taxi_axi_adapter(request, s_data_w, m_data_w): + dut = "taxi_axi_adapter" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['ADDR_W'] = 32 + parameters['S_DATA_W'] = s_data_w + parameters['S_STRB_W'] = parameters['S_DATA_W'] // 8 + parameters['S_ID_W'] = 8 + parameters['M_DATA_W'] = m_data_w + parameters['M_STRB_W'] = parameters['M_DATA_W'] // 8 + parameters['M_ID_W'] = 8 + parameters['AWUSER_EN'] = 0 + parameters['AWUSER_W'] = 1 + parameters['WUSER_EN'] = 0 + parameters['WUSER_W'] = 1 + parameters['BUSER_EN'] = 0 + parameters['BUSER_W'] = 1 + parameters['ARUSER_EN'] = 0 + parameters['ARUSER_W'] = 1 + parameters['RUSER_EN'] = 0 + parameters['RUSER_W'] = 1 + parameters['CONVERT_BURST'] = 1 + parameters['CONVERT_NARROW_BURST'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.sv b/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.sv new file mode 100644 index 0000000..d3b6510 --- /dev/null +++ b/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.sv @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 adapter testbench + */ +module test_taxi_axi_adapter # +( + /* verilator lint_off WIDTHTRUNC */ + parameter ADDR_W = 32, + parameter S_DATA_W = 32, + parameter S_STRB_W = (S_DATA_W/8), + parameter S_ID_W = 8, + parameter M_DATA_W = 32, + parameter M_STRB_W = (M_DATA_W/8), + parameter M_ID_W = 8, + parameter logic AWUSER_EN = 1'b0, + parameter AWUSER_W = 1, + parameter logic WUSER_EN = 1'b0, + parameter WUSER_W = 1, + parameter logic BUSER_EN = 1'b0, + parameter BUSER_W = 1, + parameter logic ARUSER_EN = 1'b0, + parameter ARUSER_W = 1, + parameter logic RUSER_EN = 1'b0, + parameter RUSER_W = 1, + parameter logic CONVERT_BURST = 1'b1, + parameter logic CONVERT_NARROW_BURST = 1'b0 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axi_if #( + .DATA_W(S_DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(S_STRB_W), + .ID_W(S_ID_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) s_axi(); + +taxi_axi_if #( + .DATA_W(M_DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(M_STRB_W), + .ID_W(M_ID_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) m_axi(); + +taxi_axi_adapter #( + .CONVERT_BURST(CONVERT_BURST), + .CONVERT_NARROW_BURST(CONVERT_NARROW_BURST) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_wr(s_axi), + .s_axi_rd(s_axi), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi), + .m_axi_rd(m_axi) +); + +endmodule + +`resetall