diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f new file mode 100644 index 0000000..fee5a03 --- /dev/null +++ b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f @@ -0,0 +1,3 @@ +taxi_eth_mac_1g_rgmii_fifo.sv +taxi_eth_mac_1g_rgmii.f +../axis/taxi_axis_async_fifo_adapter.f diff --git a/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv new file mode 100644 index 0000000..39decca --- /dev/null +++ b/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 1G Ethernet MAC with RGMII interface and TX and RX FIFOs + */ +module taxi_eth_mac_1g_rgmii_fifo # +( + parameter logic SIM = 1'b0, + parameter VENDOR = "XILINX", + parameter FAMILY = "virtex7", + parameter logic USE_CLK90 = 1'b1, + parameter logic PADDING_EN = 1'b1, + parameter MIN_FRAME_LEN = 64, + parameter TX_FIFO_DEPTH = 4096, + parameter TX_FIFO_RAM_PIPELINE = 1, + parameter logic TX_FRAME_FIFO = 1'b1, + parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, + parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, + parameter logic TX_DROP_WHEN_FULL = 1'b0, + parameter TX_CPL_FIFO_DEPTH = 64, + parameter RX_FIFO_DEPTH = 4096, + parameter RX_FIFO_RAM_PIPELINE = 1, + parameter logic RX_FRAME_FIFO = 1'b1, + parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, + parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, + parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME +) +( + input wire logic gtx_clk, + input wire logic gtx_clk90, + input wire logic gtx_rst, + input wire logic logic_clk, + input wire logic logic_rst, + + /* + * Transmit interface (AXI stream) + */ + taxi_axis_if.snk s_axis_tx, + taxi_axis_if.src m_axis_tx_cpl, + + /* + * Receive interface (AXI stream) + */ + taxi_axis_if.src m_axis_rx, + + /* + * RGMII interface + */ + input wire logic rgmii_rx_clk, + input wire logic [3:0] rgmii_rxd, + input wire logic rgmii_rx_ctl, + output wire logic rgmii_tx_clk, + output wire logic [3:0] rgmii_txd, + output wire logic rgmii_tx_ctl, + + /* + * Status + */ + output wire logic tx_error_underflow, + output wire logic tx_fifo_overflow, + output wire logic tx_fifo_bad_frame, + output wire logic tx_fifo_good_frame, + output wire logic rx_error_bad_frame, + output wire logic rx_error_bad_fcs, + output wire logic rx_fifo_overflow, + output wire logic rx_fifo_bad_frame, + output wire logic rx_fifo_good_frame, + output wire logic [1:0] link_speed, + + /* + * Configuration + */ + input wire logic [7:0] cfg_ifg = 8'd12, + input wire logic cfg_tx_enable = 1'b1, + input wire logic cfg_rx_enable = 1'b1 +); + +localparam PTP_TS_EN = 1'b0; +localparam PTP_TS_W = 96; + +localparam TX_USER_W = 1; +localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; +localparam TX_TAG_W = s_axis_tx.ID_W; + +wire tx_clk; +wire rx_clk; +wire tx_rst; +wire rx_rst; + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int(); +taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_cpl_int(); +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int(); + +// synchronize MAC status signals into logic clock domain +wire tx_error_underflow_int; + +logic [0:0] tx_sync_reg_1 = '0; +logic [0:0] tx_sync_reg_2 = '0; +logic [0:0] tx_sync_reg_3 = '0; +logic [0:0] tx_sync_reg_4 = '0; + +assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0]; + +always_ff @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_sync_reg_1 <= '0; + end else begin + tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int}; + end +end + +always_ff @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + tx_sync_reg_2 <= '0; + tx_sync_reg_3 <= '0; + tx_sync_reg_4 <= '0; + end else begin + tx_sync_reg_2 <= tx_sync_reg_1; + tx_sync_reg_3 <= tx_sync_reg_2; + tx_sync_reg_4 <= tx_sync_reg_3; + end +end + +wire rx_error_bad_frame_int; +wire rx_error_bad_fcs_int; + +logic [1:0] rx_sync_reg_1 = '0; +logic [1:0] rx_sync_reg_2 = '0; +logic [1:0] rx_sync_reg_3 = '0; +logic [1:0] rx_sync_reg_4 = '0; + +assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0]; +assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1]; + +always_ff @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + rx_sync_reg_1 <= '0; + end else begin + rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int}; + end +end + +always_ff @(posedge logic_clk or posedge logic_rst) begin + if (logic_rst) begin + rx_sync_reg_2 <= '0; + rx_sync_reg_3 <= '0; + rx_sync_reg_4 <= '0; + end else begin + rx_sync_reg_2 <= rx_sync_reg_1; + rx_sync_reg_3 <= rx_sync_reg_2; + rx_sync_reg_4 <= rx_sync_reg_3; + end +end + +wire [1:0] link_speed_int; + +reg [1:0] link_speed_sync_reg_1 = 2'b10; +reg [1:0] link_speed_sync_reg_2 = 2'b10; + +assign link_speed = link_speed_sync_reg_2; + +always @(posedge logic_clk) begin + link_speed_sync_reg_1 <= link_speed_int; + link_speed_sync_reg_2 <= link_speed_sync_reg_1; +end + +taxi_eth_mac_1g_rgmii #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .USE_CLK90(USE_CLK90), + .PADDING_EN(PADDING_EN), + .MIN_FRAME_LEN(MIN_FRAME_LEN), + .PTP_TS_EN(1'b0), + .PFC_EN(1'b0), + .PAUSE_EN(1'b0) +) +eth_mac_1g_rgmii_inst ( + .gtx_clk(gtx_clk), + .gtx_clk90(gtx_clk90), + .gtx_rst(gtx_rst), + .tx_clk(tx_clk), + .tx_rst(tx_rst), + .rx_clk(rx_clk), + .rx_rst(rx_rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_tx_int), + .m_axis_tx_cpl(axis_tx_cpl_int), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_rx_int), + + /* + * RGMII interface + */ + .rgmii_rx_clk(rgmii_rx_clk), + .rgmii_rxd(rgmii_rxd), + .rgmii_rx_ctl(rgmii_rx_ctl), + .rgmii_tx_clk(rgmii_tx_clk), + .rgmii_txd(rgmii_txd), + .rgmii_tx_ctl(rgmii_tx_ctl), + + /* + * PTP + */ + .tx_ptp_ts(0), + .rx_ptp_ts(0), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req(0), + .tx_lfc_resend(0), + .rx_lfc_en(0), + .rx_lfc_req(), + .rx_lfc_ack(0), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req(0), + .tx_pfc_resend(0), + .rx_pfc_en(0), + .rx_pfc_req(), + .rx_pfc_ack(0), + + /* + * Pause interface + */ + .tx_lfc_pause_en(0), + .tx_pause_req(0), + .tx_pause_ack(), + + /* + * Status + */ + .tx_start_packet(), + .tx_error_underflow(tx_error_underflow_int), + .rx_start_packet(), + .rx_error_bad_frame(rx_error_bad_frame_int), + .rx_error_bad_fcs(rx_error_bad_fcs_int), + .link_speed(link_speed_int), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable), + .cfg_mcf_rx_eth_dst_mcast(0), + .cfg_mcf_rx_check_eth_dst_mcast(0), + .cfg_mcf_rx_eth_dst_ucast(0), + .cfg_mcf_rx_check_eth_dst_ucast(0), + .cfg_mcf_rx_eth_src(0), + .cfg_mcf_rx_check_eth_src(0), + .cfg_mcf_rx_eth_type(0), + .cfg_mcf_rx_opcode_lfc(0), + .cfg_mcf_rx_check_opcode_lfc(0), + .cfg_mcf_rx_opcode_pfc(0), + .cfg_mcf_rx_check_opcode_pfc(0), + .cfg_mcf_rx_forward(0), + .cfg_mcf_rx_enable(0), + .cfg_tx_lfc_eth_dst(0), + .cfg_tx_lfc_eth_src(0), + .cfg_tx_lfc_eth_type(0), + .cfg_tx_lfc_opcode(0), + .cfg_tx_lfc_en(0), + .cfg_tx_lfc_quanta(0), + .cfg_tx_lfc_refresh(0), + .cfg_tx_pfc_eth_dst(0), + .cfg_tx_pfc_eth_src(0), + .cfg_tx_pfc_eth_type(0), + .cfg_tx_pfc_opcode(0), + .cfg_tx_pfc_en(0), + .cfg_tx_pfc_quanta(0), + .cfg_tx_pfc_refresh(0), + .cfg_rx_lfc_opcode(0), + .cfg_rx_lfc_en(0), + .cfg_rx_pfc_opcode(0), + .cfg_rx_pfc_en(0) +); + +taxi_axis_async_fifo_adapter #( + .DEPTH(TX_FIFO_DEPTH), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), + .FRAME_FIFO(TX_FRAME_FIFO), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME), + .DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) +) +tx_fifo ( + /* + * AXI4-Stream input (sink) + */ + .s_clk(logic_clk), + .s_rst(logic_rst), + .s_axis(s_axis_tx), + + /* + * AXI4-Stream output (source) + */ + .m_clk(tx_clk), + .m_rst(tx_rst), + .m_axis(axis_tx_int), + + /* + * Pause + */ + .s_pause_req(1'b0), + .s_pause_ack(), + .m_pause_req(1'b0), + .m_pause_ack(), + + /* + * Status + */ + .s_status_depth(), + .s_status_depth_commit(), + .s_status_overflow(tx_fifo_overflow), + .s_status_bad_frame(tx_fifo_bad_frame), + .s_status_good_frame(tx_fifo_good_frame), + .m_status_depth(), + .m_status_depth_commit(), + .m_status_overflow(), + .m_status_bad_frame(), + .m_status_good_frame() +); + +taxi_axis_async_fifo #( + .DEPTH(TX_CPL_FIFO_DEPTH), + .FRAME_FIFO(1'b0) +) +tx_cpl_fifo ( + /* + * AXI4-Stream input (sink) + */ + .s_clk(tx_clk), + .s_rst(tx_rst), + .s_axis(axis_tx_cpl_int), + + /* + * AXI4-Stream output (source) + */ + .m_clk(logic_clk), + .m_rst(logic_rst), + .m_axis(m_axis_tx_cpl), + + /* + * Pause + */ + .s_pause_req(1'b0), + .s_pause_ack(), + .m_pause_req(1'b0), + .m_pause_ack(), + + /* + * Status + */ + .s_status_depth(), + .s_status_depth_commit(), + .s_status_overflow(), + .s_status_bad_frame(), + .s_status_good_frame(), + .m_status_depth(), + .m_status_depth_commit(), + .m_status_overflow(), + .m_status_bad_frame(), + .m_status_good_frame() +); + +taxi_axis_async_fifo_adapter #( + .DEPTH(RX_FIFO_DEPTH), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), + .FRAME_FIFO(RX_FRAME_FIFO), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME), + .DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) +) +rx_fifo ( + /* + * AXI4-Stream input (sink) + */ + .s_clk(rx_clk), + .s_rst(rx_rst), + .s_axis(axis_rx_int), + + /* + * AXI4-Stream output (source) + */ + .m_clk(logic_clk), + .m_rst(logic_rst), + .m_axis(m_axis_rx), + + /* + * Pause + */ + .s_pause_req(1'b0), + .s_pause_ack(), + .m_pause_req(1'b0), + .m_pause_ack(), + + /* + * Status + */ + .s_status_depth(), + .s_status_depth_commit(), + .s_status_overflow(), + .s_status_bad_frame(), + .s_status_good_frame(), + .m_status_depth(), + .m_status_depth_commit(), + .m_status_overflow(rx_fifo_overflow), + .m_status_bad_frame(rx_fifo_bad_frame), + .m_status_good_frame(rx_fifo_good_frame) +); + +endmodule + +`resetall diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile new file mode 100644 index 0000000..b602782 --- /dev/null +++ b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_eth_mac_1g_rgmii_fifo +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := 1 +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"virtex7\"" +export PARAM_USE_CLK90 := 1 +export PARAM_AXIS_DATA_W := 8 +export PARAM_PADDING_EN := 1 +export PARAM_MIN_FRAME_LEN := 64 +export PARAM_TX_TAG_W := 16 +export PARAM_TX_FIFO_DEPTH := 16384 +export PARAM_TX_FIFO_RAM_PIPELINE := 1 +export PARAM_TX_FRAME_FIFO := 1 +export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO) +export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME) +export PARAM_TX_DROP_WHEN_FULL := 0 +export PARAM_TX_CPL_FIFO_DEPTH := 64 +export PARAM_RX_FIFO_DEPTH := 16384 +export PARAM_RX_FIFO_RAM_PIPELINE := 1 +export PARAM_RX_FRAME_FIFO := 1 +export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) +export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) +export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py new file mode 100644 index 0000000..3bd150d --- /dev/null +++ b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py @@ -0,0 +1,248 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.eth import GmiiFrame, RgmiiPhy +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink + + +class TB: + def __init__(self, dut, speed=1000e6): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start()) + + self.rgmii_phy = RgmiiPhy(dut.rgmii_txd, dut.rgmii_tx_ctl, dut.rgmii_tx_clk, + dut.rgmii_rxd, dut.rgmii_rx_ctl, dut.rgmii_rx_clk, speed=speed) + + self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst) + self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst) + self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst) + + dut.cfg_ifg.setimmediatevalue(0) + dut.cfg_tx_enable.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) + + dut.gtx_clk.setimmediatevalue(0) + dut.gtx_clk90.setimmediatevalue(0) + + cocotb.start_soon(self._run_gtx_clk()) + + async def reset(self): + self.dut.gtx_rst.setimmediatevalue(0) + self.dut.logic_rst.setimmediatevalue(0) + await RisingEdge(self.dut.gtx_clk) + await RisingEdge(self.dut.gtx_clk) + self.dut.gtx_rst.value = 1 + self.dut.logic_rst.value = 1 + await RisingEdge(self.dut.gtx_clk) + await RisingEdge(self.dut.gtx_clk) + self.dut.gtx_rst.value = 0 + self.dut.logic_rst.value = 0 + await RisingEdge(self.dut.gtx_clk) + await RisingEdge(self.dut.gtx_clk) + + async def _run_gtx_clk(self): + t = Timer(2, 'ns') + while True: + self.dut.gtx_clk.value = 1 + await t + self.dut.gtx_clk90.value = 1 + await t + self.dut.gtx_clk.value = 0 + await t + self.dut.gtx_clk90.value = 0 + await t + + +async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6): + + tb = TB(dut, speed) + + tb.rgmii_phy.rx.ifg = ifg + tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_rx_enable.value = 1 + + await tb.reset() + + for k in range(100): + await RisingEdge(dut.rgmii_rx_clk) + + if speed == 10e6: + assert dut.link_speed == 0 + elif speed == 100e6: + assert dut.link_speed == 1 + else: + assert dut.link_speed == 2 + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + test_frame = GmiiFrame.from_payload(test_data) + await tb.rgmii_phy.rx.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.axis_sink.recv() + + assert rx_frame.tdata == test_data + assert rx_frame.tuser == 0 + + assert tb.axis_sink.empty() + + await RisingEdge(dut.logic_clk) + await RisingEdge(dut.logic_clk) + + +async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6): + + tb = TB(dut, speed) + + tb.rgmii_phy.rx.ifg = ifg + tb.dut.cfg_ifg.value = ifg + tb.dut.cfg_tx_enable.value = 1 + + await tb.reset() + + for k in range(100): + await RisingEdge(dut.rgmii_rx_clk) + + if speed == 10e6: + assert dut.link_speed == 0 + elif speed == 100e6: + assert dut.link_speed == 1 + else: + assert dut.link_speed == 2 + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + await tb.axis_source.send(test_data) + + for test_data in test_frames: + rx_frame = await tb.rgmii_phy.tx.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.error is None + + assert tb.rgmii_phy.tx.empty() + + await RisingEdge(dut.logic_clk) + await RisingEdge(dut.logic_clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + for test in [run_test_rx, run_test_tx]: + + factory = TestFactory(test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.add_option("speed", [1000e6, 100e6, 10e6]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_eth_mac_1g_rgmii_fifo(request): + dut = "taxi_eth_mac_1g_rgmii_fifo" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "eth", f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = 1 + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"virtex7\"" + parameters['USE_CLK90'] = 1 + parameters['AXIS_DATA_W'] = 8 + parameters['PADDING_EN'] = 1 + parameters['MIN_FRAME_LEN'] = 64 + parameters['TX_TAG_W'] = 16 + parameters['TX_FIFO_DEPTH'] = 16384 + parameters['TX_FIFO_RAM_PIPELINE'] = 1 + parameters['TX_FRAME_FIFO'] = 1 + parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO'] + parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME'] + parameters['TX_DROP_WHEN_FULL'] = 0 + parameters['TX_CPL_FIFO_DEPTH'] = 64 + parameters['RX_FIFO_DEPTH'] = 16384 + parameters['RX_FIFO_RAM_PIPELINE'] = 1 + parameters['RX_FRAME_FIFO'] = 1 + parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO'] + parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME'] + parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME'] + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv new file mode 100644 index 0000000..7f105f3 --- /dev/null +++ b/tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 1G Ethernet MAC with RGMII interface and TX and RX FIFOs testbench + */ +module test_taxi_eth_mac_1g_rgmii_fifo # +( + /* verilator lint_off WIDTHTRUNC */ + parameter logic SIM = 1'b1, + parameter VENDOR = "XILINX", + parameter FAMILY = "virtex7", + parameter logic USE_CLK90 = 1'b1, + parameter AXIS_DATA_W = 8, + parameter logic PADDING_EN = 1'b1, + parameter MIN_FRAME_LEN = 64, + parameter TX_TAG_W = 16, + parameter TX_FIFO_DEPTH = 4096, + parameter TX_FIFO_RAM_PIPELINE = 1, + parameter logic TX_FRAME_FIFO = 1'b1, + parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, + parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, + parameter logic TX_DROP_WHEN_FULL = 1'b0, + parameter TX_CPL_FIFO_DEPTH = 64, + parameter RX_FIFO_DEPTH = 4096, + parameter RX_FIFO_RAM_PIPELINE = 1, + parameter logic RX_FRAME_FIFO = 1'b1, + parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, + parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, + parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam DATA_W = 8; +localparam TX_USER_W = 1; +localparam RX_USER_W = 1; + +logic gtx_clk; +logic gtx_clk90; +logic gtx_rst; +logic logic_clk; +logic logic_rst; + +taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx(); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl(); +taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx(); + +logic rgmii_rx_clk; +logic [3:0] rgmii_rxd; +logic rgmii_rx_ctl; +logic rgmii_tx_clk; +logic [3:0] rgmii_txd; +logic rgmii_tx_ctl; + +logic tx_error_underflow; +logic tx_fifo_overflow; +logic tx_fifo_bad_frame; +logic tx_fifo_good_frame; +logic rx_error_bad_frame; +logic rx_error_bad_fcs; +logic rx_fifo_overflow; +logic rx_fifo_bad_frame; +logic rx_fifo_good_frame; +logic [1:0] link_speed; + +logic [7:0] cfg_ifg; +logic cfg_tx_enable; +logic cfg_rx_enable; + +taxi_eth_mac_1g_rgmii_fifo #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .USE_CLK90(USE_CLK90), + .PADDING_EN(PADDING_EN), + .MIN_FRAME_LEN(MIN_FRAME_LEN), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), + .TX_FRAME_FIFO(TX_FRAME_FIFO), + .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME), + .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME), + .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), + .RX_FRAME_FIFO(RX_FRAME_FIFO), + .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME), + .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL) +) +uut ( + .gtx_clk(gtx_clk), + .gtx_clk90(gtx_clk90), + .gtx_rst(gtx_rst), + .logic_clk(logic_clk), + .logic_rst(logic_rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(s_axis_tx), + .m_axis_tx_cpl(m_axis_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(m_axis_rx), + + /* + * RGMII interface + */ + .rgmii_rx_clk(rgmii_rx_clk), + .rgmii_rxd(rgmii_rxd), + .rgmii_rx_ctl(rgmii_rx_ctl), + .rgmii_tx_clk(rgmii_tx_clk), + .rgmii_txd(rgmii_txd), + .rgmii_tx_ctl(rgmii_tx_ctl), + + /* + * Status + */ + .tx_error_underflow(tx_error_underflow), + .tx_fifo_overflow(tx_fifo_overflow), + .tx_fifo_bad_frame(tx_fifo_bad_frame), + .tx_fifo_good_frame(tx_fifo_good_frame), + .rx_error_bad_frame(rx_error_bad_frame), + .rx_error_bad_fcs(rx_error_bad_fcs), + .rx_fifo_overflow(rx_fifo_overflow), + .rx_fifo_bad_frame(rx_fifo_bad_frame), + .rx_fifo_good_frame(rx_fifo_good_frame), + .link_speed(link_speed), + + /* + * Configuration + */ + .cfg_ifg(cfg_ifg), + .cfg_tx_enable(cfg_tx_enable), + .cfg_rx_enable(cfg_rx_enable) +); + +endmodule + +`resetall