From 952232ad66fa4cd7e5c60c9599f45e9ed283a563 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 30 Sep 2025 15:25:21 -0700 Subject: [PATCH] apb: Add APB dual-port RAM module and testbench Signed-off-by: Alex Forencich --- README.md | 1 + src/apb/rtl/taxi_apb_dp_ram.sv | 186 +++++++++++++ src/apb/tb/taxi_apb_dp_ram/Makefile | 54 ++++ .../taxi_apb_dp_ram/test_taxi_apb_dp_ram.py | 261 ++++++++++++++++++ .../taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv | 62 +++++ 5 files changed, 564 insertions(+) create mode 100644 src/apb/rtl/taxi_apb_dp_ram.sv create mode 100644 src/apb/tb/taxi_apb_dp_ram/Makefile create mode 100644 src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.py create mode 100644 src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv diff --git a/README.md b/README.md index 765744f..9442740 100644 --- a/README.md +++ b/README.md @@ -27,6 +27,7 @@ To facilitate the dual-license model, contributions to the project can only be a * APB * SV interface for APB * Single-port RAM + * Dual-port RAM * AXI * SV interface for AXI * AXI to AXI lite adapter diff --git a/src/apb/rtl/taxi_apb_dp_ram.sv b/src/apb/rtl/taxi_apb_dp_ram.sv new file mode 100644 index 0000000..fc5d801 --- /dev/null +++ b/src/apb/rtl/taxi_apb_dp_ram.sv @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * APM RAM + */ +module taxi_apb_dp_ram # +( + // Width of address bus in bits + parameter ADDR_W = 16, + // Extra pipeline register on output + parameter logic PIPELINE_OUTPUT = 1'b0 +) +( + /* + * Port A + */ + input wire logic a_clk, + input wire logic a_rst, + taxi_apb_if.slv s_apb_a, + + /* + * Port B + */ + input wire logic b_clk, + input wire logic b_rst, + taxi_apb_if.slv s_apb_b +); + +// extract parameters +localparam DATA_W = s_apb_a.DATA_W; +localparam STRB_W = s_apb_a.STRB_W; + +localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W); +localparam BYTE_LANES = STRB_W; +localparam BYTE_W = DATA_W/BYTE_LANES; + +// check configuration +if (BYTE_W * STRB_W != DATA_W) + $fatal(0, "Error: APB data width not evenly divisible (instance %m)"); + +if (2**$clog2(BYTE_LANES) != BYTE_LANES) + $fatal(0, "Error: APB byte lane count must be even power of two (instance %m)"); + +if (s_apb_a.DATA_W != s_apb_b.DATA_W) + $fatal(0, "Error: APB interface configuration mismatch (instance %m)"); + +if (s_apb_a.ADDR_W < ADDR_W || s_apb_a.ADDR_W < ADDR_W) + $fatal(0, "Error: APB address width is insufficient (instance %m)"); + +logic mem_wr_en_a; +logic mem_rd_en_a; + +logic mem_wr_en_b; +logic mem_rd_en_b; + +logic s_apb_a_pready_reg = 1'b0, s_apb_a_pready_next; +logic s_apb_a_pready_pipe_reg = 1'b0; +logic [DATA_W-1:0] s_apb_a_prdata_reg = '0, s_apb_a_prdata_next; +logic [DATA_W-1:0] s_apb_a_prdata_pipe_reg = '0; + +logic s_apb_b_pready_reg = 1'b0, s_apb_b_pready_next; +logic s_apb_b_pready_pipe_reg = 1'b0; +logic [DATA_W-1:0] s_apb_b_prdata_reg = '0, s_apb_b_prdata_next; +logic [DATA_W-1:0] s_apb_b_prdata_pipe_reg = '0; + +// verilator lint_off MULTIDRIVEN +// (* RAM_STYLE="BLOCK" *) +logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; +// verilator lint_on MULTIDRIVEN + +wire [VALID_ADDR_W-1:0] s_apb_a_paddr_valid = VALID_ADDR_W'(s_apb_a.paddr >> (ADDR_W - VALID_ADDR_W)); +wire [VALID_ADDR_W-1:0] s_apb_b_paddr_valid = VALID_ADDR_W'(s_apb_b.paddr >> (ADDR_W - VALID_ADDR_W)); + +assign s_apb_a.prdata = PIPELINE_OUTPUT ? s_apb_a_prdata_pipe_reg : s_apb_a_prdata_reg; +assign s_apb_a.pready = PIPELINE_OUTPUT ? s_apb_a_pready_pipe_reg : s_apb_a_pready_reg; +assign s_apb_a.pslverr = 1'b0; +assign s_apb_a.pruser = '0; +assign s_apb_a.pbuser = '0; + +assign s_apb_b.prdata = PIPELINE_OUTPUT ? s_apb_b_prdata_pipe_reg : s_apb_b_prdata_reg; +assign s_apb_b.pready = PIPELINE_OUTPUT ? s_apb_b_pready_pipe_reg : s_apb_b_pready_reg; +assign s_apb_b.pslverr = 1'b0; +assign s_apb_b.pruser = '0; +assign s_apb_b.pbuser = '0; + +initial begin + // two nested loops for smaller number of iterations per loop + // workaround for synthesizer complaints about large loop counts + for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin + for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin + mem[j] = '0; + end + end +end + +always_comb begin + mem_wr_en_a = 1'b0; + mem_rd_en_a = 1'b0; + + s_apb_a_pready_next = 1'b0; + + if (s_apb_a.psel && s_apb_a.penable && (!s_apb_a_pready_reg && (PIPELINE_OUTPUT || !s_apb_a_pready_pipe_reg))) begin + s_apb_a_pready_next = 1'b1; + + if (s_apb_a.pwrite) begin + mem_wr_en_a = 1'b1; + end else begin + mem_rd_en_a = 1'b1; + end + end +end + +always_ff @(posedge a_clk) begin + s_apb_a_pready_reg <= s_apb_a_pready_next; + + for (integer i = 0; i < BYTE_LANES; i = i + 1) begin + if (mem_wr_en_a && s_apb_a.pstrb[i]) begin + mem[s_apb_a_paddr_valid][BYTE_W*i +: BYTE_W] <= s_apb_a.pwdata[BYTE_W*i +: BYTE_W]; + end + end + + if (mem_rd_en_a) begin + s_apb_a_prdata_reg <= mem[s_apb_a_paddr_valid]; + end + + s_apb_a_prdata_pipe_reg <= s_apb_a_prdata_reg; + s_apb_a_pready_pipe_reg <= s_apb_a_pready_reg; + + if (a_rst) begin + s_apb_a_pready_reg <= 1'b0; + end +end + +always_comb begin + mem_wr_en_b = 1'b0; + mem_rd_en_b = 1'b0; + + s_apb_b_pready_next = 1'b0; + + if (s_apb_b.psel && s_apb_b.penable && (!s_apb_b_pready_reg && (PIPELINE_OUTPUT || !s_apb_b_pready_pipe_reg))) begin + s_apb_b_pready_next = 1'b1; + + if (s_apb_b.pwrite) begin + mem_wr_en_b = 1'b1; + end else begin + mem_rd_en_b = 1'b1; + end + end +end + +always_ff @(posedge b_clk) begin + s_apb_b_pready_reg <= s_apb_b_pready_next; + + for (integer i = 0; i < BYTE_LANES; i = i + 1) begin + if (mem_wr_en_b && s_apb_b.pstrb[i]) begin + mem[s_apb_b_paddr_valid][BYTE_W*i +: BYTE_W] <= s_apb_b.pwdata[BYTE_W*i +: BYTE_W]; + end + end + + if (mem_rd_en_b) begin + s_apb_b_prdata_reg <= mem[s_apb_b_paddr_valid]; + end + + s_apb_b_prdata_pipe_reg <= s_apb_b_prdata_reg; + s_apb_b_pready_pipe_reg <= s_apb_b_pready_reg; + + if (b_rst) begin + s_apb_b_pready_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/apb/tb/taxi_apb_dp_ram/Makefile b/src/apb/tb/taxi_apb_dp_ram/Makefile new file mode 100644 index 0000000..48dec59 --- /dev/null +++ b/src/apb/tb/taxi_apb_dp_ram/Makefile @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_apb_dp_ram +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 32 +export PARAM_ADDR_W := 16 +export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_PIPELINE_OUTPUT := 0 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.py b/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.py new file mode 100644 index 0000000..34b5028 --- /dev/null +++ b/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.py @@ -0,0 +1,261 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import ApbBus, ApbMaster + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start()) + cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start()) + + self.apb_master = [] + + self.apb_master.append(ApbMaster(ApbBus.from_entity(dut.s_apb_a), dut.a_clk, dut.a_rst)) + self.apb_master.append(ApbMaster(ApbBus.from_entity(dut.s_apb_b), dut.b_clk, dut.b_rst)) + + def set_idle_generator(self, generator=None): + if generator: + for apb_master in self.apb_master: + apb_master.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.a_rst.setimmediatevalue(0) + self.dut.b_rst.setimmediatevalue(0) + await RisingEdge(self.dut.a_clk) + await RisingEdge(self.dut.a_clk) + self.dut.a_rst.value = 1 + self.dut.b_rst.value = 1 + await RisingEdge(self.dut.a_clk) + await RisingEdge(self.dut.a_clk) + self.dut.a_rst.value = 0 + await RisingEdge(self.dut.b_clk) + self.dut.b_rst.value = 0 + await RisingEdge(self.dut.a_clk) + await RisingEdge(self.dut.a_clk) + + +async def run_test_write(dut, port=0, data_in=None, idle_inserter=None): + + tb = TB(dut) + + apb_master = tb.apb_master[port] + byte_lanes = apb_master.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + await apb_master.write(addr-4, b'\xaa'*(length+8)) + + await apb_master.write(addr, test_data) + + data = await apb_master.read(addr-1, length+2) + + assert data.data == b'\xaa'+test_data+b'\xaa' + + await RisingEdge(dut.a_clk) + await RisingEdge(dut.a_clk) + + +async def run_test_read(dut, port=0, data_in=None, idle_inserter=None): + + tb = TB(dut) + + apb_master = tb.apb_master[port] + byte_lanes = apb_master.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + await apb_master.write(addr, test_data) + + data = await apb_master.read(addr, length) + + assert data.data == test_data + + await RisingEdge(dut.a_clk) + await RisingEdge(dut.a_clk) + + +async def run_test_arb(dut, data_in=None, idle_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + async def worker(master, offset): + wr_op = master.init_write(offset, b'\x11\x22\x33\x44') + rd_op = master.init_read(offset, 4) + + await wr_op.wait() + await rd_op.wait() + + workers = [] + + for k in range(10): + workers.append(cocotb.start_soon(worker(tb.apb_master[0], k*256))) + workers.append(cocotb.start_soon(worker(tb.apb_master[1], k*256))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.a_clk) + await RisingEdge(dut.a_clk) + + +async def run_stress_test(dut, idle_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.apb_master[k%len(tb.apb_master)], k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.a_clk) + await RisingEdge(dut.a_clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("port", [0, 1]) + factory.generate_tests() + + factory = TestFactory(run_test_arb) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("data_w", [8, 16, 32]) +def test_taxi_apb_dp_ram(request, data_w): + dut = "taxi_apb_dp_ram" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_apb_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = data_w + parameters['ADDR_W'] = 16 + parameters['STRB_W'] = parameters['DATA_W'] // 8 + parameters['PIPELINE_OUTPUT'] = 0 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv b/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv new file mode 100644 index 0000000..2e05457 --- /dev/null +++ b/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * APB dual-port RAM testbench + */ +module test_taxi_apb_dp_ram # +( + /* verilator lint_off WIDTHTRUNC */ + parameter DATA_W = 32, + parameter ADDR_W = 16, + parameter STRB_W = (DATA_W/8), + parameter PIPELINE_OUTPUT = 0 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic a_clk; +logic a_rst; +logic b_clk; +logic b_rst; + +taxi_apb_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W+16), + .STRB_W(STRB_W) +) s_apb_a(), s_apb_b(); + +taxi_apb_dp_ram #( + .ADDR_W(ADDR_W), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT) +) +uut ( + /* + * Port A + */ + .a_clk(a_clk), + .a_rst(a_rst), + .s_apb_a(s_apb_a), + + /* + * Port B + */ + .b_clk(b_clk), + .b_rst(b_rst), + .s_apb_b(s_apb_b) +); + +endmodule + +`resetall