diff --git a/src/cndm/tb/cndm_micro_pcie_us/Makefile b/src/cndm/tb/cndm_micro_pcie_us/Makefile
index eee83fc..e19a906 100644
--- a/src/cndm/tb/cndm_micro_pcie_us/Makefile
+++ b/src/cndm/tb/cndm_micro_pcie_us/Makefile
@@ -24,9 +24,6 @@ MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
 VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
-VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
-VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
-VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
diff --git a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py
index 3812ca4..cb17441 100644
--- a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py
+++ b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py
@@ -499,9 +499,6 @@ def test_cndm_micro_pcie_us(request, mac_data_w):
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
         os.path.join(rtl_dir, f"{dut}.f"),
-        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
-        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
-        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)