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cndm: Remove extraneous files from testbench file lists

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-06 18:04:14 -08:00
parent ce8da1bc59
commit 96630b8f61
2 changed files with 0 additions and 6 deletions
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3
src/cndm/tb/cndm_micro_pcie_us/Makefile
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@@ -24,9 +24,6 @@ MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL) TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
# handle file list files # handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

3
src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py
View File

@@ -499,9 +499,6 @@ def test_cndm_micro_pcie_us(request, mac_data_w):
verilog_sources = [ verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"), os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"), os.path.join(rtl_dir, f"{dut}.f"),
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
] ]
verilog_sources = process_f_files(verilog_sources) verilog_sources = process_f_files(verilog_sources)