From 98d06954cceb0c5068df7a9dc83899b3a35619ec Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 13 Jun 2025 10:28:53 -0700 Subject: [PATCH] eth: Avoid hardcoding clock period Signed-off-by: Alex Forencich --- .../taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py | 8 ++++---- src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py | 2 +- .../taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py | 2 +- .../tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py | 2 +- .../test_taxi_eth_mac_phy_10g_fifo.py | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py b/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py index 3de6ecd..bc822ac 100644 --- a/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py +++ b/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py @@ -145,7 +145,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i if rx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - rx_frame_sfd_ns -= 3.2 + rx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) @@ -155,7 +155,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i assert rx_frame.check_fcs() assert rx_frame.ctrl is None if gbx_cfg is None: - assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01 + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01 assert tb.sink.empty() @@ -222,7 +222,7 @@ async def run_test_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12): if rx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - rx_frame_sfd_ns -= 3.2 + rx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) @@ -232,7 +232,7 @@ async def run_test_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12): assert rx_frame.check_fcs() assert rx_frame.ctrl is None if gbx_cfg is None: - assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01 + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01 start_lane.append(rx_frame.start_lane) diff --git a/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py b/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py index 2e3c750..5fc9527 100644 --- a/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py +++ b/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py @@ -252,7 +252,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): if rx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - rx_frame_sfd_ns -= 3.2 + rx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) diff --git a/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py b/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py index 8a5ba7b..08f0a1f 100644 --- a/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py +++ b/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py @@ -227,7 +227,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): if rx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - rx_frame_sfd_ns -= 3.2 + rx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) diff --git a/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py b/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py index 54510a2..0bda598 100644 --- a/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py +++ b/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py @@ -297,7 +297,7 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12): if rx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - rx_frame_sfd_ns -= 3.2 + rx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) diff --git a/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py index 04cc62c..ebe5e87 100644 --- a/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py +++ b/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py @@ -273,7 +273,7 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12): if rx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - rx_frame_sfd_ns -= 3.2 + rx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)