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zircon: Add FIFO configuration parameters

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-13 17:17:34 -07:00
parent af8daa89ce
commit 9955b79fcd
4 changed files with 27 additions and 19 deletions
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10
src/zircon/rtl/zircon_ip_rx_egress.sv
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@@ -17,7 +17,9 @@ Authors:
*/ */
module zircon_ip_rx_egress # module zircon_ip_rx_egress #
( (
parameter N_UI = 4 parameter N_UI = 4,
parameter UI_RX_FIFO_DEPTH = 32,
parameter logic UI_RX_FIFO_EB_MODE = 1'b1
) )
( (
input wire logic clk, input wire logic clk,
@@ -41,14 +43,14 @@ localparam DATA_W = s_axis_pkt.DATA_W;
// RX FIFO // RX FIFO
taxi_axis_async_fifo #( taxi_axis_async_fifo #(
.DEPTH((UI_DATA_W > DATA_W ? UI_DATA_W : DATA_W)/8*32), .DEPTH(UI_RX_FIFO_EB_MODE ? (UI_DATA_W > DATA_W ? UI_DATA_W : DATA_W)/8*UI_RX_FIFO_DEPTH : UI_RX_FIFO_DEPTH),
.RAM_PIPELINE(1), .RAM_PIPELINE(1),
.OUTPUT_FIFO_EN(1'b0), .OUTPUT_FIFO_EN(1'b0),
.FRAME_FIFO(1'b0), .FRAME_FIFO(1'b0),
.USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1), .USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(1'b0), .DROP_OVERSIZE_FRAME(!UI_RX_FIFO_EB_MODE),
.DROP_BAD_FRAME(1'b0), .DROP_BAD_FRAME(!UI_RX_FIFO_EB_MODE),
.DROP_WHEN_FULL(1'b0), .DROP_WHEN_FULL(1'b0),
.MARK_WHEN_FULL(1'b0), .MARK_WHEN_FULL(1'b0),
.PAUSE_EN(1'b0) .PAUSE_EN(1'b0)

16
src/zircon/rtl/zircon_ip_rx_ingress.sv
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@@ -18,7 +18,9 @@ Authors:
module zircon_ip_rx_ingress # module zircon_ip_rx_ingress #
( (
parameter logic IPV6_EN = 1'b1, parameter logic IPV6_EN = 1'b1,
parameter logic HASH_EN = 1'b1 parameter logic HASH_EN = 1'b1,
parameter MAC_RX_FIFO_DEPTH = 32,
parameter logic MAC_RX_FIFO_EB_MODE = 1'b1
) )
( (
input wire logic clk, input wire logic clk,
@@ -49,16 +51,16 @@ taxi_axis_if #(.DATA_W(32), .USER_EN(1), .USER_W(RX_USER_W)) rx_pkt_hdr();
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) rx_bcast_int[2](); taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) rx_bcast_int[2]();
taxi_axis_async_fifo_adapter #( taxi_axis_async_fifo_adapter #(
.DEPTH((MAC_DATA_W > DATA_W ? MAC_DATA_W : DATA_W)/8*32), .DEPTH(MAC_RX_FIFO_EB_MODE ? (MAC_DATA_W > DATA_W ? MAC_DATA_W : DATA_W)/8*MAC_RX_FIFO_DEPTH : MAC_RX_FIFO_DEPTH),
.RAM_PIPELINE(1), .RAM_PIPELINE(1),
.OUTPUT_FIFO_EN(1'b0), .OUTPUT_FIFO_EN(1'b0),
.FRAME_FIFO(1'b0), .FRAME_FIFO(!MAC_RX_FIFO_EB_MODE),
.USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1), .USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(1'b0), .DROP_OVERSIZE_FRAME(!MAC_RX_FIFO_EB_MODE),
.DROP_BAD_FRAME(1'b0), .DROP_BAD_FRAME(!MAC_RX_FIFO_EB_MODE),
.DROP_WHEN_FULL(1'b0), .DROP_WHEN_FULL(!MAC_RX_FIFO_EB_MODE),
.MARK_WHEN_FULL(1'b1), .MARK_WHEN_FULL(MAC_RX_FIFO_EB_MODE),
.PAUSE_EN(1'b0) .PAUSE_EN(1'b0)
) )
rx_fifo_inst ( rx_fifo_inst (

10
src/zircon/rtl/zircon_ip_tx_egress.sv
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@@ -17,7 +17,9 @@ Authors:
*/ */
module zircon_ip_tx_egress # module zircon_ip_tx_egress #
( (
parameter logic IPV6_EN = 1'b1 parameter logic IPV6_EN = 1'b1,
parameter MAC_TX_FIFO_DEPTH = 32,
parameter logic MAC_TX_FIFO_EB_MODE = 1'b1
) )
( (
input wire logic clk, input wire logic clk,
@@ -116,14 +118,14 @@ tx_hdr_concat_inst (
// TX FIFO // TX FIFO
taxi_axis_async_fifo #( taxi_axis_async_fifo #(
.DEPTH((MAC_DATA_W > DATA_W ? MAC_DATA_W : DATA_W)/8*32), .DEPTH(MAC_TX_FIFO_EB_MODE ? (MAC_DATA_W > DATA_W ? MAC_DATA_W : DATA_W)/8*MAC_TX_FIFO_DEPTH : MAC_TX_FIFO_DEPTH),
.RAM_PIPELINE(1), .RAM_PIPELINE(1),
.OUTPUT_FIFO_EN(1'b0), .OUTPUT_FIFO_EN(1'b0),
.FRAME_FIFO(1'b1), .FRAME_FIFO(1'b1),
.USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1), .USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(1'b0), .DROP_OVERSIZE_FRAME(!MAC_TX_FIFO_EB_MODE),
.DROP_BAD_FRAME(1'b0), .DROP_BAD_FRAME(!MAC_TX_FIFO_EB_MODE),
.DROP_WHEN_FULL(1'b0), .DROP_WHEN_FULL(1'b0),
.MARK_WHEN_FULL(1'b0), .MARK_WHEN_FULL(1'b0),
.PAUSE_EN(1'b0) .PAUSE_EN(1'b0)

10
src/zircon/rtl/zircon_ip_tx_ingress.sv
View File

@@ -17,7 +17,9 @@ Authors:
*/ */
module zircon_ip_tx_ingress # module zircon_ip_tx_ingress #
( (
parameter N_UI = 4 parameter N_UI = 4,
parameter UI_TX_FIFO_DEPTH = 32,
parameter logic UI_TX_FIFO_EB_MODE = 1'b1
) )
( (
input wire logic clk, input wire logic clk,
@@ -42,14 +44,14 @@ localparam DATA_W = m_axis_pkt.DATA_W;
// TX FIFO // TX FIFO
taxi_axis_async_fifo #( taxi_axis_async_fifo #(
.DEPTH((UI_DATA_W > DATA_W ? UI_DATA_W : DATA_W)/8*32), .DEPTH(UI_TX_FIFO_EB_MODE ? (UI_DATA_W > DATA_W ? UI_DATA_W : DATA_W)/8*UI_TX_FIFO_DEPTH : UI_TX_FIFO_DEPTH),
.RAM_PIPELINE(1), .RAM_PIPELINE(1),
.OUTPUT_FIFO_EN(1'b0), .OUTPUT_FIFO_EN(1'b0),
.FRAME_FIFO(1'b0), .FRAME_FIFO(1'b0),
.USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1), .USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(1'b0), .DROP_OVERSIZE_FRAME(!UI_TX_FIFO_EB_MODE),
.DROP_BAD_FRAME(1'b0), .DROP_BAD_FRAME(!UI_TX_FIFO_EB_MODE),
.DROP_WHEN_FULL(1'b0), .DROP_WHEN_FULL(1'b0),
.MARK_WHEN_FULL(1'b0), .MARK_WHEN_FULL(1'b0),
.PAUSE_EN(1'b0) .PAUSE_EN(1'b0)