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pcie: Cast widths in VPD implementation

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-02-20 22:14:01 -08:00
parent 63c9544c3f
commit 9b55a08465
1 changed files with 4 additions and 4 deletions
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8
src/pcie/rtl/taxi_pcie_us_vpd.sv
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@@ -101,20 +101,20 @@ always_comb begin
end end
if (cfg_ext_read_received) begin if (cfg_ext_read_received) begin
if (cfg_ext_register_number == (CAP_OFFSET >> 2)) begin if (cfg_ext_register_number == 10'(CAP_OFFSET >> 2)) begin
cfg_ext_read_data_next[7:0] = CAP_ID; cfg_ext_read_data_next[7:0] = CAP_ID;
cfg_ext_read_data_next[15:8] = CAP_NEXT; cfg_ext_read_data_next[15:8] = CAP_NEXT;
cfg_ext_read_data_next[30:16] = addr_reg; cfg_ext_read_data_next[30:16] = addr_reg;
cfg_ext_read_data_next[31] = flag_reg; cfg_ext_read_data_next[31] = flag_reg;
cfg_ext_read_data_valid_next = 1'b1; cfg_ext_read_data_valid_next = 1'b1;
end else if (cfg_ext_register_number == (CAP_OFFSET >> 2)+1) begin end else if (cfg_ext_register_number == 10'(CAP_OFFSET >> 2)+1) begin
cfg_ext_read_data_next = data_reg; cfg_ext_read_data_next = data_reg;
cfg_ext_read_data_valid_next = 1'b1; cfg_ext_read_data_valid_next = 1'b1;
end end
end end
if (cfg_ext_write_received && !m_apb_psel_reg) begin if (cfg_ext_write_received && !m_apb_psel_reg) begin
if (cfg_ext_register_number == (CAP_OFFSET >> 2)) begin if (cfg_ext_register_number == 10'(CAP_OFFSET >> 2)) begin
addr_next = cfg_ext_write_data[30:16]; addr_next = cfg_ext_write_data[30:16];
flag_next = cfg_ext_write_data[31]; flag_next = cfg_ext_write_data[31];
@@ -127,7 +127,7 @@ always_comb begin
m_apb_psel_next = 1'b1; m_apb_psel_next = 1'b1;
m_apb_pwrite_next = 1'b0; m_apb_pwrite_next = 1'b0;
end end
end else if (cfg_ext_register_number == (CAP_OFFSET >> 2)+1) begin end else if (cfg_ext_register_number == 10'(CAP_OFFSET >> 2)+1) begin
data_next = cfg_ext_write_data; data_next = cfg_ext_write_data;
end end
end end