From 9d701c918693d47a02dad6d60685a4b38f5f839c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 8 Mar 2026 14:40:38 -0700 Subject: [PATCH] axi: Clean up array init Signed-off-by: Alex Forencich --- src/axi/rtl/taxi_axi_crossbar_addr.sv | 12 ++++-------- src/axi/rtl/taxi_axi_ram.sv | 12 +----------- src/axi/rtl/taxi_axil_crossbar_rd.sv | 21 +++------------------ src/axi/rtl/taxi_axil_crossbar_wr.sv | 19 +++---------------- src/axi/rtl/taxi_axil_dp_ram.sv | 12 +----------- src/axi/rtl/taxi_axil_ram.sv | 12 +----------- 6 files changed, 13 insertions(+), 75 deletions(-) diff --git a/src/axi/rtl/taxi_axi_crossbar_addr.sv b/src/axi/rtl/taxi_axi_crossbar_addr.sv index 6015a92..f6a6dc7 100644 --- a/src/axi/rtl/taxi_axi_crossbar_addr.sv +++ b/src/axi/rtl/taxi_axi_crossbar_addr.sv @@ -251,10 +251,10 @@ logic [TR_CNT_W-1:0] trans_count_reg = 0; wire trans_limit = trans_count_reg >= TR_CNT_W'(S_ACCEPT) && !trans_complete; // transfer ID thread tracking -logic [ID_W-1:0] thread_id_reg[S_INT_THREADS-1:0]; -logic [SEL_W-1:0] thread_m_reg[S_INT_THREADS-1:0]; -logic [3:0] thread_region_reg[S_INT_THREADS-1:0]; -logic [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0]; +logic [ID_W-1:0] thread_id_reg[S_INT_THREADS-1:0] = '{default: '0}; +logic [SEL_W-1:0] thread_m_reg[S_INT_THREADS-1:0] = '{default: '0}; +logic [3:0] thread_region_reg[S_INT_THREADS-1:0] = '{default: '0}; +logic [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0] = '{default: '0}; // TODO fix loop /* verilator lint_off UNOPTFLAT */ @@ -266,10 +266,6 @@ wire [S_INT_THREADS-1:0] thread_trans_start; wire [S_INT_THREADS-1:0] thread_trans_complete; for (genvar n = 0; n < S_INT_THREADS; n = n + 1) begin - initial begin - thread_count_reg[n] = '0; - end - assign thread_active[n] = thread_count_reg[n] != 0; assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid; assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next); diff --git a/src/axi/rtl/taxi_axi_ram.sv b/src/axi/rtl/taxi_axi_ram.sv index a7caaca..0ee73a8 100644 --- a/src/axi/rtl/taxi_axi_ram.sv +++ b/src/axi/rtl/taxi_axi_ram.sv @@ -100,7 +100,7 @@ logic s_axi_rlast_pipe_reg = 1'b0; logic s_axi_rvalid_pipe_reg = 1'b0; // (* RAM_STYLE="BLOCK" *) -logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; +logic [DATA_W-1:0] mem[2**VALID_ADDR_W] = '{default: '0}; wire [VALID_ADDR_W-1:0] read_addr_valid = VALID_ADDR_W'(read_addr_reg >> (ADDR_W - VALID_ADDR_W)); wire [VALID_ADDR_W-1:0] write_addr_valid = VALID_ADDR_W'(write_addr_reg >> (ADDR_W - VALID_ADDR_W)); @@ -120,16 +120,6 @@ assign s_axi_rd.rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg assign s_axi_rd.ruser = '0; assign s_axi_rd.rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg; -initial begin - // two nested loops for smaller number of iterations per loop - // workaround for synthesizer complaints about large loop counts - for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin - for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin - mem[j] = '0; - end - end -end - always_comb begin write_state_next = WRITE_STATE_IDLE; diff --git a/src/axi/rtl/taxi_axil_crossbar_rd.sv b/src/axi/rtl/taxi_axil_crossbar_rd.sv index b51efa1..b5a6eba 100644 --- a/src/axi/rtl/taxi_axil_crossbar_rd.sv +++ b/src/axi/rtl/taxi_axil_crossbar_rd.sv @@ -155,9 +155,9 @@ for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = 0; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW] = '{default: '0}; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - logic fifo_decerr[2**FIFO_AW]; + logic fifo_decerr[2**FIFO_AW] = '{default: '0}; wire [CL_M_COUNT_INT-1:0] fifo_wr_select; wire fifo_wr_decerr; @@ -171,15 +171,6 @@ for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; - integer i; - - initial begin - for (i = 0; i < 2**FIFO_AW; i = i + 1) begin - fifo_select[i] = 0; - fifo_decerr[i] = 0; - end - end - always_ff @(posedge clk) begin if (fifo_wr_en) begin fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; @@ -321,7 +312,7 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW] = '{default: '0}; wire [CL_S_COUNT_INT-1:0] fifo_wr_select; wire fifo_wr_en; wire fifo_rd_en; @@ -329,12 +320,6 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; - initial begin - for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin - fifo_select[i] = '0; - end - end - always_ff @(posedge clk) begin if (fifo_wr_en) begin fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; diff --git a/src/axi/rtl/taxi_axil_crossbar_wr.sv b/src/axi/rtl/taxi_axil_crossbar_wr.sv index 3c36d8f..b1bffa6 100644 --- a/src/axi/rtl/taxi_axil_crossbar_wr.sv +++ b/src/axi/rtl/taxi_axil_crossbar_wr.sv @@ -172,9 +172,9 @@ for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW] = '{default: '0}; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - logic fifo_decerr[2**FIFO_AW]; + logic fifo_decerr[2**FIFO_AW] = '{default: '0}; wire [CL_M_COUNT_INT-1:0] fifo_wr_select; wire fifo_wr_decerr; @@ -188,13 +188,6 @@ for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; - initial begin - for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin - fifo_select[i] = '0; - fifo_decerr[i] = '0; - end - end - always_ff @(posedge clk) begin if (fifo_wr_en) begin fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; @@ -382,7 +375,7 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW] = '{default: '0}; wire [CL_S_COUNT_INT-1:0] fifo_wr_select; wire fifo_wr_en; wire fifo_rd_en; @@ -390,12 +383,6 @@ for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; - initial begin - for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin - fifo_select[i] = '0; - end - end - always_ff @(posedge clk) begin if (fifo_wr_en) begin fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; diff --git a/src/axi/rtl/taxi_axil_dp_ram.sv b/src/axi/rtl/taxi_axil_dp_ram.sv index 268e930..badf103 100644 --- a/src/axi/rtl/taxi_axil_dp_ram.sv +++ b/src/axi/rtl/taxi_axil_dp_ram.sv @@ -96,7 +96,7 @@ logic s_axil_b_rvalid_pipe_reg = 1'b0; // verilator lint_off MULTIDRIVEN // (* RAM_STYLE="BLOCK" *) -logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; +logic [DATA_W-1:0] mem[2**VALID_ADDR_W] = '{default: '0}; // verilator lint_on MULTIDRIVEN wire [VALID_ADDR_W-1:0] s_axil_a_awaddr_valid = VALID_ADDR_W'(s_axil_wr_a.awaddr >> (ADDR_W - VALID_ADDR_W)); @@ -129,16 +129,6 @@ assign s_axil_rd_b.rresp = 2'b00; assign s_axil_rd_b.ruser = '0; assign s_axil_rd_b.rvalid = PIPELINE_OUTPUT ? s_axil_b_rvalid_pipe_reg : s_axil_b_rvalid_reg; -initial begin - // two nested loops for smaller number of iterations per loop - // workaround for synthesizer complaints about large loop counts - for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin - for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin - mem[j] = 0; - end - end -end - always_comb begin mem_wr_en_a = 1'b0; mem_rd_en_a = 1'b0; diff --git a/src/axi/rtl/taxi_axil_ram.sv b/src/axi/rtl/taxi_axil_ram.sv index 4bc9e6a..aea9928 100644 --- a/src/axi/rtl/taxi_axil_ram.sv +++ b/src/axi/rtl/taxi_axil_ram.sv @@ -67,7 +67,7 @@ logic [DATA_W-1:0] s_axil_rdata_pipe_reg = '0; logic s_axil_rvalid_pipe_reg = 1'b0; // (* RAM_STYLE="BLOCK" *) -logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; +logic [DATA_W-1:0] mem[2**VALID_ADDR_W] = '{default: '0}; wire [VALID_ADDR_W-1:0] s_axil_awaddr_valid = VALID_ADDR_W'(s_axil_wr.awaddr >> (ADDR_W - VALID_ADDR_W)); wire [VALID_ADDR_W-1:0] s_axil_araddr_valid = VALID_ADDR_W'(s_axil_rd.araddr >> (ADDR_W - VALID_ADDR_W)); @@ -84,16 +84,6 @@ assign s_axil_rd.rresp = 2'b00; assign s_axil_rd.ruser = '0; assign s_axil_rd.rvalid = PIPELINE_OUTPUT ? s_axil_rvalid_pipe_reg : s_axil_rvalid_reg; -initial begin - // two nested loops for smaller number of iterations per loop - // workaround for synthesizer complaints about large loop counts - for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin - for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin - mem[j] = '0; - end - end -end - always_comb begin mem_wr_en = 1'b0;