diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index 03e2b32..bccd0a0 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -146,7 +146,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n; assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p; assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CNT = 4; diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index a263fa3..8783175 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -46,48 +47,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.user_sw.setimmediatevalue(0) diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index 191b9f0..0db81cb 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -249,7 +249,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT]; wire eth_gty_rst[GTY_CLK_CNT]; -for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk +for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk wire eth_gty_mgt_refclk_int; @@ -297,7 +297,7 @@ end localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; -for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad +for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad localparam CLK = n; localparam CNT = 4; diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index 35586c5..d3efdf0 100644 --- a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -51,48 +52,47 @@ class TB: for clk in dut.eth_gty_mgt_refclk_p: cocotb.start_soon(Clock(clk, 6.4, units="ns").start()) - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.sw.setimmediatevalue(0) dut.eth_port_modprsl.setimmediatevalue(0) diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index 226e75f..7191bbb 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -317,7 +317,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT]; wire eth_gty_rst[GTY_CLK_CNT]; -for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk +for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk wire eth_gty_mgt_refclk_int; @@ -378,7 +378,7 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP13[4] = '{"QSFP13.1", "QSFP13.2", localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP14[4] = '{"QSFP14.1", "QSFP14.2", "QSFP14.3", "QSFP14.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP15[4] = '{"QSFP15.1", "QSFP15.2", "QSFP15.3", "QSFP15.4"}; -for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad +for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad localparam CLK = n; localparam CNT = 4; diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py index 5b91c84..160991d 100644 --- a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -52,48 +53,47 @@ class TB: for clk in dut.eth_gty_mgt_refclk_p: cocotb.start_soon(Clock(clk, 6.206, units="ns").start()) - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.i2c_scl_i.setimmediatevalue(1) dut.i2c_sda_i.setimmediatevalue(1) diff --git a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv index 16dbd3b..51453c4 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv @@ -161,7 +161,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n; assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p; assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CNT = 4; diff --git a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py index 02e06a0..f3b2451 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -46,48 +47,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.qsfp_0_modprsl.setimmediatevalue(0) dut.qsfp_0_intl.setimmediatevalue(0) diff --git a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv index 2e423d3..118f167 100644 --- a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv @@ -550,7 +550,7 @@ assign qsfp_rx_n[4*1 +: 4] = qsfp2_rx_n; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CNT = 4; diff --git a/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py index 4a017a0..40bcdad 100644 --- a/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -57,48 +58,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.phy_gmii_clk_en.setimmediatevalue(1) diff --git a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv index 0b7c2d3..7190771 100644 --- a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv @@ -215,7 +215,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT]; wire eth_gty_rst[GTY_CLK_CNT]; -for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk +for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk wire eth_gty_mgt_refclk_int; @@ -277,7 +277,7 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "Q localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP3[4] = '{"QSFP3.1", "QSFP3.2", "QSFP3.3", "QSFP3.4"}; -for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad +for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad localparam CNT = 4; diff --git a/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py index 8b06a6b..6252d5c 100644 --- a/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -52,48 +53,47 @@ class TB: for clk in dut.eth_gty_mgt_refclk_p: cocotb.start_soon(Clock(clk, 3.102, units="ns").start()) - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) async def init(self): diff --git a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv index 9858ba2..743865d 100644 --- a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv @@ -135,7 +135,7 @@ wire qsfp_mgt_refclk_bufg[2]; wire qsfp_rst[2]; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk +for (genvar n = 0; n < 2; n = n + 1) begin : gt_clk wire qsfp_mgt_refclk_int; @@ -192,7 +192,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n; assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p; assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CLK = n; localparam CNT = 4; diff --git a/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index 664fe5b..86c72a6 100644 --- a/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -47,48 +48,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.qsfp_0_mod_prsnt_n.setimmediatevalue(0) dut.qsfp_0_intr_n.setimmediatevalue(0)