From 9ec5bd019078a4a658c82ed56666cf27382449da Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 8 Mar 2026 14:43:14 -0700 Subject: [PATCH] ptp: Clean up array init Signed-off-by: Alex Forencich --- src/ptp/rtl/taxi_ptp_clock.sv | 25 ++++++----------------- src/ptp/rtl/taxi_ptp_clock_cdc.sv | 34 ++++++++----------------------- 2 files changed, 14 insertions(+), 45 deletions(-) diff --git a/src/ptp/rtl/taxi_ptp_clock.sv b/src/ptp/rtl/taxi_ptp_clock.sv index 5a3badb..e780666 100644 --- a/src/ptp/rtl/taxi_ptp_clock.sv +++ b/src/ptp/rtl/taxi_ptp_clock.sv @@ -128,17 +128,17 @@ if (PIPELINE_OUTPUT > 0) begin // pipeline (* shreg_extract = "no" *) - logic [95:0] output_ts_tod_reg[0:PIPELINE_OUTPUT-1]; + logic [95:0] output_ts_tod_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_ts_tod_step_reg[0:PIPELINE_OUTPUT-1]; + logic output_ts_tod_step_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic [63:0] output_ts_rel_reg[0:PIPELINE_OUTPUT-1]; + logic [63:0] output_ts_rel_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_ts_rel_step_reg[0:PIPELINE_OUTPUT-1]; + logic output_ts_rel_step_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_pps_reg[0:PIPELINE_OUTPUT-1]; + logic output_pps_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_pps_str_reg[0:PIPELINE_OUTPUT-1]; + logic output_pps_str_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; assign output_ts_tod = output_ts_tod_reg[PIPELINE_OUTPUT-1]; assign output_ts_tod_step = output_ts_tod_step_reg[PIPELINE_OUTPUT-1]; @@ -149,19 +149,6 @@ if (PIPELINE_OUTPUT > 0) begin assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1]; assign output_pps_str = output_pps_str_reg[PIPELINE_OUTPUT-1]; - initial begin - for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin - output_ts_tod_reg[i] = '0; - output_ts_tod_step_reg[i] = 1'b0; - - output_ts_rel_reg[i] = '0; - output_ts_rel_step_reg[i] = 1'b0; - - output_pps_reg[i] = 1'b0; - output_pps_str_reg[i] = 1'b0; - end - end - always_ff @(posedge clk) begin output_ts_tod_reg[0][95:48] <= ts_tod_s_reg; output_ts_tod_reg[0][47:46] <= 2'b00; diff --git a/src/ptp/rtl/taxi_ptp_clock_cdc.sv b/src/ptp/rtl/taxi_ptp_clock_cdc.sv index c6b0751..46adfed 100644 --- a/src/ptp/rtl/taxi_ptp_clock_cdc.sv +++ b/src/ptp/rtl/taxi_ptp_clock_cdc.sv @@ -106,10 +106,10 @@ logic ts_step_reg = 1'b0, ts_step_next; logic pps_reg = 1'b0; logic pps_str_reg = 1'b0; -logic [47:0] ts_s_pipe_reg[0:PIPELINE_OUTPUT-1]; -logic [TS_NS_W+CMP_FNS_W-1:0] ts_ns_pipe_reg[0:PIPELINE_OUTPUT-1]; -logic ts_step_pipe_reg[0:PIPELINE_OUTPUT-1]; -logic pps_pipe_reg[0:PIPELINE_OUTPUT-1]; +logic [47:0] ts_s_pipe_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; +logic [TS_NS_W+CMP_FNS_W-1:0] ts_ns_pipe_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; +logic ts_step_pipe_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; +logic pps_pipe_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; logic [PHASE_CNT_W-1:0] src_phase_reg = '0; logic [PHASE_ACC_W-1:0] dest_phase_reg = '0, dest_phase_next; @@ -151,28 +151,19 @@ if (PIPELINE_OUTPUT > 0) begin // pipeline (* shreg_extract = "no" *) - logic [TS_W-1:0] output_ts_reg[0:PIPELINE_OUTPUT-1]; + logic [TS_W-1:0] output_ts_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_ts_step_reg[0:PIPELINE_OUTPUT-1]; + logic output_ts_step_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_pps_reg[0:PIPELINE_OUTPUT-1]; + logic output_pps_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; (* shreg_extract = "no" *) - logic output_pps_str_reg[0:PIPELINE_OUTPUT-1]; + logic output_pps_str_reg[0:PIPELINE_OUTPUT-1] = '{default: '0}; assign output_ts = output_ts_reg[PIPELINE_OUTPUT-1]; assign output_ts_step = output_ts_step_reg[PIPELINE_OUTPUT-1]; assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1]; assign output_pps_str = output_pps_str_reg[PIPELINE_OUTPUT-1]; - initial begin - for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin - output_ts_reg[i] = 0; - output_ts_step_reg[i] = 1'b0; - output_pps_reg[i] = 1'b0; - output_pps_str_reg[i] = 1'b0; - end - end - always_ff @(posedge output_clk) begin if (TS_W == 96) begin output_ts_reg[0][95:48] <= ts_s_reg; @@ -220,15 +211,6 @@ end else begin end -initial begin - for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin - ts_s_pipe_reg[i] = 0; - ts_ns_pipe_reg[i] = 0; - ts_step_pipe_reg[i] = 1'b0; - pps_pipe_reg[i] = 1'b0; - end -end - // source PTP clock capture and sync logic logic input_ts_step_reg = 1'b0;