From a56a33abc9978b3c42202c0089fcc21271df847d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 19 Feb 2025 12:02:07 -0800 Subject: [PATCH] examples: Add notes on required licenses Signed-off-by: Alex Forencich --- example/Arty/fpga/README.md | 7 +++++++ example/KC705/fpga/README.md | 7 +++++++ example/KCU105/fpga/README.md | 7 +++++++ example/KR260/fpga/README.md | 7 +++++++ example/VCU108/fpga/README.md | 7 +++++++ 5 files changed, 35 insertions(+) diff --git a/example/Arty/fpga/README.md b/example/Arty/fpga/README.md index 8515e04..2d6f252 100644 --- a/example/Arty/fpga/README.md +++ b/example/Arty/fpga/README.md @@ -16,6 +16,13 @@ The design places a looped-back MAC on the BASE-T port, as well as a looped-back * FPGA: XC7A35TICSG324-1L * PHY: TI DP83848J via MII +## Licensing + +* Toolchain + * Vivado Standard (enterprise license not required) +* IP + * No licensed vendor IP or 3rd party IP + ## How to build Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. diff --git a/example/KC705/fpga/README.md b/example/KC705/fpga/README.md index 9be9297..10eba20 100644 --- a/example/KC705/fpga/README.md +++ b/example/KC705/fpga/README.md @@ -21,6 +21,13 @@ The design places looped-back MACs on both the BASE-T port as well as the SFP+ c * 1000BASE-T PHY: Marvell 88E1111 via GMII, RGMII, or SGMII * 1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver +## Licensing + +* Toolchain + * Vivado Enterprise (requires license) +* IP + * No licensed vendor IP or 3rd party IP + ## How to build Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. diff --git a/example/KCU105/fpga/README.md b/example/KCU105/fpga/README.md index 5f89af6..f56d76a 100644 --- a/example/KCU105/fpga/README.md +++ b/example/KCU105/fpga/README.md @@ -18,6 +18,13 @@ The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as * FPGA: xcku040-ffva1156-2-e * 1000BASE-T PHY: Marvell 88E1111 via SGMII +## Licensing + +* Toolchain + * Vivado Enterprise (requires license) +* IP + * No licensed vendor IP or 3rd party IP + ## How to build Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. diff --git a/example/KR260/fpga/README.md b/example/KR260/fpga/README.md index dd18826..8c6aab6 100644 --- a/example/KR260/fpga/README.md +++ b/example/KR260/fpga/README.md @@ -18,6 +18,13 @@ The design places looped-back MACs on the BASE-T ports and SFP+ cage, as well as * FPGA: xck26-sfvc784-2LV-c * 1000BASE-T PHY: Marvell 88E1111 via SGMII +## Licensing + +* Toolchain + * Vivado Standard (enterprise license not required) +* IP + * No licensed vendor IP or 3rd party IP + ## How to build Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. diff --git a/example/VCU108/fpga/README.md b/example/VCU108/fpga/README.md index 84e92e4..921fbf0 100644 --- a/example/VCU108/fpga/README.md +++ b/example/VCU108/fpga/README.md @@ -16,6 +16,13 @@ The design places a looped-back MAC on the BASE-T port as well as a looped-back * FPGA: xcvu095-ffva2104-2-e * 1000BASE-T PHY: Marvell 88E1111 via SGMII +## Licensing + +* Toolchain + * Vivado Enterprise (requires license) +* IP + * No licensed vendor IP or 3rd party IP + ## How to build Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.