diff --git a/example/Alveo/fpga/README.md b/example/Alveo/fpga/README.md index dd4c95a..1bc9f38 100644 --- a/example/Alveo/fpga/README.md +++ b/example/Alveo/fpga/README.md @@ -4,10 +4,10 @@ This example design targets the Xilinx Alveo series. -The design places looped-back MACs on the Ethernet ports as well as a looped-back UART on on the USB UART connections. +The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control. * USB UART - * Looped-back UART + * XFCP (3 Mbaud) * DSFP/QSFP28 * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers @@ -50,6 +50,4 @@ Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensu Run `make program` to program the board with Vivado. -To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification. - To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/example/Alveo/fpga/fpga_AU200/Makefile b/example/Alveo/fpga/fpga_AU200/Makefile index 46290a3..083aea0 100644 --- a/example/Alveo/fpga/fpga_AU200/Makefile +++ b/example/Alveo/fpga/fpga_AU200/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au200.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU200_10g/Makefile b/example/Alveo/fpga/fpga_AU200_10g/Makefile index b61a33b..a559084 100644 --- a/example/Alveo/fpga/fpga_AU200_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU200_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au200.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU250/Makefile b/example/Alveo/fpga/fpga_AU250/Makefile index 182bc65..1d90d47 100644 --- a/example/Alveo/fpga/fpga_AU250/Makefile +++ b/example/Alveo/fpga/fpga_AU250/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au200.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU250_10g/Makefile b/example/Alveo/fpga/fpga_AU250_10g/Makefile index 4a5b572..da86713 100644 --- a/example/Alveo/fpga/fpga_AU250_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU250_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au200.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU280/Makefile b/example/Alveo/fpga/fpga_AU280/Makefile index 664ef56..f067711 100644 --- a/example/Alveo/fpga/fpga_AU280/Makefile +++ b/example/Alveo/fpga/fpga_AU280/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au280.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU280_10g/Makefile b/example/Alveo/fpga/fpga_AU280_10g/Makefile index 29e3958..e200cde 100644 --- a/example/Alveo/fpga/fpga_AU280_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU280_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au280.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU45N/Makefile b/example/Alveo/fpga/fpga_AU45N/Makefile index ba5dae6..bc2b977 100644 --- a/example/Alveo/fpga/fpga_AU45N/Makefile +++ b/example/Alveo/fpga/fpga_AU45N/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au45n.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU45N_10g/Makefile b/example/Alveo/fpga/fpga_AU45N_10g/Makefile index 9f60462..739b3da 100644 --- a/example/Alveo/fpga/fpga_AU45N_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU45N_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au45n.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU50/Makefile b/example/Alveo/fpga/fpga_AU50/Makefile index 0ed6090..6526c75 100644 --- a/example/Alveo/fpga/fpga_AU50/Makefile +++ b/example/Alveo/fpga/fpga_AU50/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au50.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU50_10g/Makefile b/example/Alveo/fpga/fpga_AU50_10g/Makefile index 35e29d6..f8aa891 100644 --- a/example/Alveo/fpga/fpga_AU50_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU50_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au50.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU55C/Makefile b/example/Alveo/fpga/fpga_AU55C/Makefile index 221a149..4af6072 100644 --- a/example/Alveo/fpga/fpga_AU55C/Makefile +++ b/example/Alveo/fpga/fpga_AU55C/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au55.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU55C_10g/Makefile b/example/Alveo/fpga/fpga_AU55C_10g/Makefile index e30a718..d329d4a 100644 --- a/example/Alveo/fpga/fpga_AU55C_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU55C_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au55.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU55N/Makefile b/example/Alveo/fpga/fpga_AU55N/Makefile index 1716344..3a5d695 100644 --- a/example/Alveo/fpga/fpga_AU55N/Makefile +++ b/example/Alveo/fpga/fpga_AU55N/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au55.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_AU55N_10g/Makefile b/example/Alveo/fpga/fpga_AU55N_10g/Makefile index be886f6..5534bf4 100644 --- a/example/Alveo/fpga/fpga_AU55N_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU55N_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au55.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_VCU1525/Makefile b/example/Alveo/fpga/fpga_VCU1525/Makefile index 98abe78..6da773f 100644 --- a/example/Alveo/fpga/fpga_VCU1525/Makefile +++ b/example/Alveo/fpga/fpga_VCU1525/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au200.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile b/example/Alveo/fpga/fpga_VCU1525_10g/Makefile index 9818470..8819fd2 100644 --- a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile +++ b/example/Alveo/fpga/fpga_VCU1525_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_au200.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_X3522/Makefile b/example/Alveo/fpga/fpga_X3522/Makefile index a84371c..73b3c47 100644 --- a/example/Alveo/fpga/fpga_X3522/Makefile +++ b/example/Alveo/fpga/fpga_X3522/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_x3522.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/fpga_X3522_10g/Makefile b/example/Alveo/fpga/fpga_X3522_10g/Makefile index aa58e50..f69532a 100644 --- a/example/Alveo/fpga/fpga_X3522_10g/Makefile +++ b/example/Alveo/fpga/fpga_X3522_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = virtexuplus SYN_FILES = ../rtl/fpga_x3522.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/rtl/fpga_core.sv b/example/Alveo/fpga/rtl/fpga_core.sv index 59d54de..773d46b 100644 --- a/example/Alveo/fpga/rtl/fpga_core.sv +++ b/example/Alveo/fpga/rtl/fpga_core.sv @@ -72,8 +72,110 @@ module fpga_core # output wire logic [PORT_CNT-1:0] eth_port_lpmode ); -// UART -for (genvar n = 0; n < UART_CNT; n = n + 1) begin : uart_ch +// XFCP +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us(); + +taxi_xfcp_if_uart #( + .TX_FIFO_DEPTH(512), + .RX_FIFO_DEPTH(512) +) +xfcp_if_uart_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * UART interface + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd), + + /* + * XFCP downstream interface + */ + .xfcp_dsp_ds(xfcp_ds), + .xfcp_dsp_us(xfcp_us), + + /* + * Configuration + */ + .prescale(16'(125000000/3000000)) +); + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1](); + +taxi_xfcp_switch #( + .XFCP_ID_STR("Alveo"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR("Taxi example"), + .PORTS($size(xfcp_sw_us)) +) +xfcp_sw_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_ds), + .xfcp_usp_us(xfcp_us), + + /* + * XFCP downstream ports + */ + .xfcp_dsp_ds(xfcp_sw_ds), + .xfcp_dsp_us(xfcp_sw_us) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat(); + +taxi_xfcp_mod_stats #( + .XFCP_ID_STR("Statistics"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR(""), + .STAT_COUNT_W(64), + .STAT_PIPELINE(2) +) +xfcp_stats_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[0]), + .xfcp_usp_us(xfcp_sw_us[0]), + + /* + * Statistics increment input + */ + .s_axis_stat(axis_stat) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT](); + +taxi_axis_arb_mux #( + .S_COUNT($size(axis_eth_stat)), + .UPDATE_TID(1'b0), + .ARB_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIO(1'b0) +) +stat_mux_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * AXI4-Stream inputs (sink) + */ + .s_axis(axis_eth_stat), + + /* + * AXI4-Stream output (source) + */ + .m_axis(axis_stat) +); + +// Additional UARTs +for (genvar n = 1; n < UART_CNT; n = n + 1) begin : uart_ch taxi_axis_if #(.DATA_W(8)) axis_uart(); @@ -128,8 +230,6 @@ wire [GTY_CNT-1:0] eth_gty_rx_clk; wire [GTY_CNT-1:0] eth_gty_rx_rst; taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT](); -taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) eth_gty_axis_stat[GTY_QUAD_CNT](); - wire [GTY_CNT-1:0] eth_gty_rx_status; wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood; @@ -210,7 +310,11 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), .COUNT_125US(125000/6.4), - .STAT_EN(1'b0) + .STAT_EN(1), + .STAT_TX_LEVEL(1), + .STAT_RX_LEVEL(1), + .STAT_ID_BASE(n*CNT*(16+16)), + .STAT_UPDATE_PERIOD(1024) ) mac_inst ( .xcvr_ctrl_clk(clk_125mhz), @@ -293,7 +397,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad */ .stat_clk(clk_125mhz), .stat_rst(rst_125mhz), - .m_axis_stat(eth_gty_axis_stat[n]), + .m_axis_stat(axis_eth_stat[n]), /* * Status diff --git a/example/Alveo/fpga/tb/fpga_core/Makefile b/example/Alveo/fpga/tb/fpga_core/Makefile index 12753af..7870181 100644 --- a/example/Alveo/fpga/tb/fpga_core/Makefile +++ b/example/Alveo/fpga/tb/fpga_core/Makefile @@ -20,7 +20,9 @@ MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += ../../rtl/$(DUT).sv VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index 96d69c3..f02bf9c 100644 --- a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -43,8 +43,8 @@ class TB: cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) - self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1) - self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1) + self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1) + self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1) self.qsfp_sources = [] self.qsfp_sinks = [] @@ -90,25 +90,6 @@ class TB: await t -async def uart_test(tb, source, sink): - tb.log.info("Test UART") - - tx_data = b"FPGA" - - tb.log.info("UART TX: %s", tx_data) - - await source.write(tx_data) - - rx_data = bytearray() - - while len(rx_data) < len(tx_data): - rx_data.extend(await sink.read()) - - tb.log.info("UART RX: %s", rx_data) - - tb.log.info("UART test done") - - async def mac_test(tb, source, sink): tb.log.info("Test MAC") @@ -158,10 +139,6 @@ async def run_test(dut): tests = [] - tb.log.info("Start UART test") - - tests.append(cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink))) - for k in range(len(tb.qsfp_sources)): tb.log.info("Start QSFP %d MAC loopback test", k) @@ -201,7 +178,9 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),