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eth: Reorganize clock enable in BASE-R model

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-05-27 23:56:28 -07:00
parent 9bce7f4165
commit aa8f19bf3b
1 changed files with 344 additions and 338 deletions
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10
src/eth/tb/baser.py
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@@ -137,7 +137,10 @@ class BaseRSerdesSource():
while True: while True:
await RisingEdge(self.clock) await RisingEdge(self.clock)
if self.enable is None or self.enable.value: # clock enable
if self.enable is not None and not self.enable.value:
continue
if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4): if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
# in IFG # in IFG
ifg_cnt = ifg_cnt - self.byte_lanes ifg_cnt = ifg_cnt - self.byte_lanes
@@ -436,7 +439,10 @@ class BaseRSerdesSink:
while True: while True:
await RisingEdge(self.clock) await RisingEdge(self.clock)
if self.enable is None or self.enable.value: # clock enable
if self.enable is not None and not self.enable.value:
continue
data = self.data.value.integer data = self.data.value.integer
hdr = self.hdr.value.integer hdr = self.hdr.value.integer