mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 00:48:40 -08:00
eth: Reorganize clock enable in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -137,216 +137,219 @@ class BaseRSerdesSource():
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while True:
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while True:
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await RisingEdge(self.clock)
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await RisingEdge(self.clock)
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if self.enable is None or self.enable.value:
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# clock enable
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if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
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if self.enable is not None and not self.enable.value:
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# in IFG
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continue
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ifg_cnt = ifg_cnt - self.byte_lanes
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if ifg_cnt < 0:
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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elif frame is None:
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if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
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# idle
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# in IFG
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if not self.queue.empty():
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ifg_cnt = ifg_cnt - self.byte_lanes
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# send frame
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if ifg_cnt < 0:
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frame = self.queue.get_nowait()
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if self.enable_dic:
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self.dequeue_event.set()
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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self.queue_occupancy_bytes -= len(frame)
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ifg_cnt = 0
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self.queue_occupancy_frames -= 1
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self.current_frame = frame
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frame.sim_time_start = get_sim_time()
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frame.sim_time_sfd = None
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frame.sim_time_end = None
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self.log.info("TX frame: %s", frame)
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frame.normalize()
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frame.start_lane = 0
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assert frame.data[0] == EthPre.PRE
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assert frame.ctrl[0] == 0
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frame.data[0] = XgmiiCtrl.START
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frame.ctrl[0] = 1
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frame.data.append(XgmiiCtrl.TERM)
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frame.ctrl.append(1)
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# offset start
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elif frame is None:
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if self.enable_dic:
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# idle
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min_ifg = 3 - deficit_idle_cnt
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if not self.queue.empty():
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else:
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# send frame
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min_ifg = 0
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frame = self.queue.get_nowait()
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self.dequeue_event.set()
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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self.current_frame = frame
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frame.sim_time_start = get_sim_time()
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frame.sim_time_sfd = None
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frame.sim_time_end = None
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self.log.info("TX frame: %s", frame)
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frame.normalize()
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frame.start_lane = 0
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assert frame.data[0] == EthPre.PRE
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assert frame.ctrl[0] == 0
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frame.data[0] = XgmiiCtrl.START
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frame.ctrl[0] = 1
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frame.data.append(XgmiiCtrl.TERM)
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frame.ctrl.append(1)
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if self.byte_lanes > 4 and (ifg_cnt > min_ifg or self.force_offset_start):
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# offset start
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ifg_cnt = ifg_cnt-4
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if self.enable_dic:
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frame.start_lane = 4
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min_ifg = 3 - deficit_idle_cnt
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frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data
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frame.ctrl = [1]*4+frame.ctrl
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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self.active = True
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frame_offset = 0
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else:
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else:
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# clear counters
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min_ifg = 0
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deficit_idle_cnt = 0
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ifg_cnt = 0
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if frame is not None:
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if self.byte_lanes > 4 and (ifg_cnt > min_ifg or self.force_offset_start):
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dl = bytearray()
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ifg_cnt = ifg_cnt-4
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cl = []
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frame.start_lane = 4
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frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data
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frame.ctrl = [1]*4+frame.ctrl
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for k in range(self.byte_lanes):
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if self.enable_dic:
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if frame is not None:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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d = frame.data[frame_offset]
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ifg_cnt = 0
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if frame.sim_time_sfd is None and d == EthPre.SFD:
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self.active = True
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frame.sim_time_sfd = get_sim_time()
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frame_offset = 0
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dl.append(d)
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else:
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cl.append(frame.ctrl[frame_offset])
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# clear counters
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frame_offset += 1
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deficit_idle_cnt = 0
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ifg_cnt = 0
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if frame_offset >= len(frame.data):
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if frame is not None:
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ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0)
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dl = bytearray()
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frame.sim_time_end = get_sim_time()
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cl = []
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frame.handle_tx_complete()
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frame = None
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self.current_frame = None
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else:
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dl.append(XgmiiCtrl.IDLE)
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cl.append(1)
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# remap control characters
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for k in range(self.byte_lanes):
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ctrl = sum(xgmii_ctrl_to_baser_mapping.get(d, BaseRCtrl.ERROR) << i*7 for i, d in enumerate(dl))
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if frame is not None:
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d = frame.data[frame_offset]
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if frame.sim_time_sfd is None and d == EthPre.SFD:
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frame.sim_time_sfd = get_sim_time()
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dl.append(d)
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cl.append(frame.ctrl[frame_offset])
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frame_offset += 1
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if not any(cl):
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if frame_offset >= len(frame.data):
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# data
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ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0)
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hdr = BaseRSync.DATA
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frame.sim_time_end = get_sim_time()
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data = int.from_bytes(dl, 'little')
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frame.handle_tx_complete()
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frame = None
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self.current_frame = None
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else:
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else:
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# control
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dl.append(XgmiiCtrl.IDLE)
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hdr = BaseRSync.CTRL
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cl.append(1)
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if cl[0] and dl[0] == XgmiiCtrl.START and not any(cl[1:]):
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# start in lane 0
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data = BaseRBlockType.START_0
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for i in range(1, 8):
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data |= dl[i] << i*8
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elif cl[4] and dl[4] == XgmiiCtrl.START and not any(cl[5:]):
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# start in lane 4
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if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
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# ordered set in lane 0
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data = BaseRBlockType.OS_START
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for i in range(1, 4):
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data |= dl[i] << i*8
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if dl[0] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 32
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else:
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# other control
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data = BaseRBlockType.START_4 | (ctrl & 0xfffffff) << 8
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for i in range(5, 8):
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# remap control characters
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data |= dl[i] << i*8
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ctrl = sum(xgmii_ctrl_to_baser_mapping.get(d, BaseRCtrl.ERROR) << i*7 for i, d in enumerate(dl))
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elif cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
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if not any(cl):
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# data
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hdr = BaseRSync.DATA
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data = int.from_bytes(dl, 'little')
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else:
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# control
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hdr = BaseRSync.CTRL
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if cl[0] and dl[0] == XgmiiCtrl.START and not any(cl[1:]):
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# start in lane 0
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data = BaseRBlockType.START_0
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for i in range(1, 8):
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data |= dl[i] << i*8
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elif cl[4] and dl[4] == XgmiiCtrl.START and not any(cl[5:]):
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# start in lane 4
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if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
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# ordered set in lane 0
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# ordered set in lane 0
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if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
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data = BaseRBlockType.OS_START
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# ordered set in lane 4
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data = BaseRBlockType.OS_04
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for i in range(5, 8):
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data |= dl[i] << i*8
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if dl[4] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 36
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else:
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data = BaseRBlockType.OS_0 | (ctrl & 0xfffffff) << 40
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for i in range(1, 4):
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for i in range(1, 4):
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data |= dl[i] << i*8
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data |= dl[i] << i*8
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if dl[0] == XgmiiCtrl.SIG_OS:
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if dl[0] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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# signal ordered set
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data |= BaseRO.SIG_OS << 32
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data |= BaseRO.SIG_OS << 32
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elif cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
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else:
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# other control
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data = BaseRBlockType.START_4 | (ctrl & 0xfffffff) << 8
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for i in range(5, 8):
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data |= dl[i] << i*8
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elif cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
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# ordered set in lane 0
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if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
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# ordered set in lane 4
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# ordered set in lane 4
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data = BaseRBlockType.OS_4 | (ctrl & 0xfffffff) << 8
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data = BaseRBlockType.OS_04
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for i in range(5, 8):
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for i in range(5, 8):
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data |= dl[i] << i*8
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data |= dl[i] << i*8
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if dl[4] == XgmiiCtrl.SIG_OS:
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if dl[4] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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# signal ordered set
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data |= BaseRO.SIG_OS << 36
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data |= BaseRO.SIG_OS << 36
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elif cl[0] and dl[0] == XgmiiCtrl.TERM:
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# terminate in lane 0
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data = BaseRBlockType.TERM_0 | (ctrl & 0xffffffffffff80) << 8
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elif cl[1] and dl[1] == XgmiiCtrl.TERM and not cl[0]:
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# terminate in lane 1
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data = BaseRBlockType.TERM_1 | (ctrl & 0xffffffffffc000) << 8 | dl[0] << 8
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elif cl[2] and dl[2] == XgmiiCtrl.TERM and not any(cl[0:2]):
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# terminate in lane 2
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data = BaseRBlockType.TERM_2 | (ctrl & 0xffffffffe00000) << 8
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for i in range(2):
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data |= dl[i] << ((i+1)*8)
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elif cl[3] and dl[3] == XgmiiCtrl.TERM and not any(cl[0:3]):
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# terminate in lane 3
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data = BaseRBlockType.TERM_3 | (ctrl & 0xfffffff0000000) << 8
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for i in range(3):
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data |= dl[i] << ((i+1)*8)
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elif cl[4] and dl[4] == XgmiiCtrl.TERM and not any(cl[0:4]):
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# terminate in lane 4
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data = BaseRBlockType.TERM_4 | (ctrl & 0xfffff800000000) << 8
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for i in range(4):
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data |= dl[i] << ((i+1)*8)
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elif cl[5] and dl[5] == XgmiiCtrl.TERM and not any(cl[0:5]):
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# terminate in lane 5
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data = BaseRBlockType.TERM_5 | (ctrl & 0xfffc0000000000) << 8
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for i in range(5):
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data |= dl[i] << ((i+1)*8)
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elif cl[6] and dl[6] == XgmiiCtrl.TERM and not any(cl[0:6]):
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# terminate in lane 6
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data = BaseRBlockType.TERM_6 | (ctrl & 0xfe000000000000) << 8
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for i in range(6):
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data |= dl[i] << ((i+1)*8)
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elif cl[7] and dl[7] == XgmiiCtrl.TERM and not any(cl[0:7]):
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# terminate in lane 7
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data = BaseRBlockType.TERM_7
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for i in range(7):
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data |= dl[i] << ((i+1)*8)
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else:
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else:
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# all control
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data = BaseRBlockType.OS_0 | (ctrl & 0xfffffff) << 40
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data = BaseRBlockType.CTRL | ctrl << 8
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for i in range(1, 4):
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else:
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data |= dl[i] << i*8
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data = BaseRBlockType.CTRL
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if dl[0] == XgmiiCtrl.SIG_OS:
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hdr = BaseRSync.CTRL
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# signal ordered set
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self.active = False
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data |= BaseRO.SIG_OS << 32
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self.idle_event.set()
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elif cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
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# ordered set in lane 4
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data = BaseRBlockType.OS_4 | (ctrl & 0xfffffff) << 8
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for i in range(5, 8):
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data |= dl[i] << i*8
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if dl[4] == XgmiiCtrl.SIG_OS:
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# signal ordered set
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data |= BaseRO.SIG_OS << 36
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elif cl[0] and dl[0] == XgmiiCtrl.TERM:
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# terminate in lane 0
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data = BaseRBlockType.TERM_0 | (ctrl & 0xffffffffffff80) << 8
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elif cl[1] and dl[1] == XgmiiCtrl.TERM and not cl[0]:
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# terminate in lane 1
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data = BaseRBlockType.TERM_1 | (ctrl & 0xffffffffffc000) << 8 | dl[0] << 8
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elif cl[2] and dl[2] == XgmiiCtrl.TERM and not any(cl[0:2]):
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# terminate in lane 2
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data = BaseRBlockType.TERM_2 | (ctrl & 0xffffffffe00000) << 8
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for i in range(2):
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data |= dl[i] << ((i+1)*8)
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elif cl[3] and dl[3] == XgmiiCtrl.TERM and not any(cl[0:3]):
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# terminate in lane 3
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data = BaseRBlockType.TERM_3 | (ctrl & 0xfffffff0000000) << 8
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for i in range(3):
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data |= dl[i] << ((i+1)*8)
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elif cl[4] and dl[4] == XgmiiCtrl.TERM and not any(cl[0:4]):
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# terminate in lane 4
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data = BaseRBlockType.TERM_4 | (ctrl & 0xfffff800000000) << 8
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for i in range(4):
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data |= dl[i] << ((i+1)*8)
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elif cl[5] and dl[5] == XgmiiCtrl.TERM and not any(cl[0:5]):
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# terminate in lane 5
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data = BaseRBlockType.TERM_5 | (ctrl & 0xfffc0000000000) << 8
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for i in range(5):
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data |= dl[i] << ((i+1)*8)
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elif cl[6] and dl[6] == XgmiiCtrl.TERM and not any(cl[0:6]):
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# terminate in lane 6
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data = BaseRBlockType.TERM_6 | (ctrl & 0xfe000000000000) << 8
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for i in range(6):
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data |= dl[i] << ((i+1)*8)
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elif cl[7] and dl[7] == XgmiiCtrl.TERM and not any(cl[0:7]):
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# terminate in lane 7
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data = BaseRBlockType.TERM_7
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for i in range(7):
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data |= dl[i] << ((i+1)*8)
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else:
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# all control
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data = BaseRBlockType.CTRL | ctrl << 8
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else:
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data = BaseRBlockType.CTRL
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hdr = BaseRSync.CTRL
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self.active = False
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self.idle_event.set()
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if self.scramble:
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if self.scramble:
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# 64b/66b scrambler
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# 64b/66b scrambler
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b = 0
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b = 0
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for i in range(len(self.data)):
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for i in range(len(self.data)):
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if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
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if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
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scrambler_state = ((scrambler_state & 0x1ffffffffffffff) << 1) | 1
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scrambler_state = ((scrambler_state & 0x1ffffffffffffff) << 1) | 1
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b = b | (1 << i)
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b = b | (1 << i)
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else:
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else:
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scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1
|
scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1
|
||||||
data = b
|
data = b
|
||||||
|
|
||||||
if self.slip is not None and self.slip.value:
|
if self.slip is not None and self.slip.value:
|
||||||
self.bit_offset += 1
|
self.bit_offset += 1
|
||||||
|
|
||||||
self.bit_offset = max(0, self.bit_offset) % 66
|
self.bit_offset = max(0, self.bit_offset) % 66
|
||||||
|
|
||||||
if self.bit_offset != 0:
|
if self.bit_offset != 0:
|
||||||
d = data << 2 | hdr
|
d = data << 2 | hdr
|
||||||
|
|
||||||
out_d = ((last_d | d << 66) >> 66-self.bit_offset) & 0x3ffffffffffffffff
|
out_d = ((last_d | d << 66) >> 66-self.bit_offset) & 0x3ffffffffffffffff
|
||||||
|
|
||||||
last_d = d
|
last_d = d
|
||||||
|
|
||||||
data = out_d >> 2
|
data = out_d >> 2
|
||||||
hdr = out_d & 3
|
hdr = out_d & 3
|
||||||
|
|
||||||
if self.reverse:
|
if self.reverse:
|
||||||
# bit reverse
|
# bit reverse
|
||||||
data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
|
data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
|
||||||
hdr = sum(1 << (1-i) for i in range(2) if (hdr >> i) & 1)
|
hdr = sum(1 << (1-i) for i in range(2) if (hdr >> i) & 1)
|
||||||
|
|
||||||
self.data.value = data
|
self.data.value = data
|
||||||
self.hdr.value = hdr
|
self.hdr.value = hdr
|
||||||
|
|
||||||
|
|
||||||
class BaseRSerdesSink:
|
class BaseRSerdesSink:
|
||||||
@@ -436,178 +439,181 @@ class BaseRSerdesSink:
|
|||||||
while True:
|
while True:
|
||||||
await RisingEdge(self.clock)
|
await RisingEdge(self.clock)
|
||||||
|
|
||||||
if self.enable is None or self.enable.value:
|
# clock enable
|
||||||
data = self.data.value.integer
|
if self.enable is not None and not self.enable.value:
|
||||||
hdr = self.hdr.value.integer
|
continue
|
||||||
|
|
||||||
if self.reverse:
|
data = self.data.value.integer
|
||||||
# bit reverse
|
hdr = self.hdr.value.integer
|
||||||
data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
|
|
||||||
hdr = sum(1 << (1-i) for i in range(2) if (hdr >> i) & 1)
|
|
||||||
|
|
||||||
if self.scramble:
|
if self.reverse:
|
||||||
# 64b/66b descrambler
|
# bit reverse
|
||||||
b = 0
|
data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
|
||||||
for i in range(len(self.data)):
|
hdr = sum(1 << (1-i) for i in range(2) if (hdr >> i) & 1)
|
||||||
if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
|
|
||||||
b = b | (1 << i)
|
|
||||||
scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 | bool(data & (1 << i))
|
|
||||||
data = b
|
|
||||||
|
|
||||||
# 10GBASE-R decoding
|
if self.scramble:
|
||||||
|
# 64b/66b descrambler
|
||||||
|
b = 0
|
||||||
|
for i in range(len(self.data)):
|
||||||
|
if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
|
||||||
|
b = b | (1 << i)
|
||||||
|
scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 | bool(data & (1 << i))
|
||||||
|
data = b
|
||||||
|
|
||||||
# remap control characters
|
# 10GBASE-R decoding
|
||||||
ctrl = bytearray(baser_ctrl_to_xgmii_mapping.get((data >> i*7+8) & 0x7f, XgmiiCtrl.ERROR) for i in range(8))
|
|
||||||
|
|
||||||
data = data.to_bytes(8, 'little')
|
# remap control characters
|
||||||
|
ctrl = bytearray(baser_ctrl_to_xgmii_mapping.get((data >> i*7+8) & 0x7f, XgmiiCtrl.ERROR) for i in range(8))
|
||||||
|
|
||||||
dl = bytearray()
|
data = data.to_bytes(8, 'little')
|
||||||
cl = []
|
|
||||||
if hdr == BaseRSync.DATA:
|
dl = bytearray()
|
||||||
# data
|
cl = []
|
||||||
dl = data
|
if hdr == BaseRSync.DATA:
|
||||||
cl = [0]*8
|
# data
|
||||||
elif hdr == BaseRSync.CTRL:
|
dl = data
|
||||||
if data[0] == BaseRBlockType.CTRL:
|
cl = [0]*8
|
||||||
# C7 C6 C5 C4 C3 C2 C1 C0 BT
|
elif hdr == BaseRSync.CTRL:
|
||||||
dl = ctrl
|
if data[0] == BaseRBlockType.CTRL:
|
||||||
cl = [1]*8
|
# C7 C6 C5 C4 C3 C2 C1 C0 BT
|
||||||
elif data[0] == BaseRBlockType.OS_4:
|
dl = ctrl
|
||||||
# D7 D6 D5 O4 C3 C2 C1 C0 BT
|
cl = [1]*8
|
||||||
dl = ctrl[0:4]
|
elif data[0] == BaseRBlockType.OS_4:
|
||||||
cl = [1]*4
|
# D7 D6 D5 O4 C3 C2 C1 C0 BT
|
||||||
if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
|
dl = ctrl[0:4]
|
||||||
dl.append(XgmiiCtrl.SEQ_OS)
|
cl = [1]*4
|
||||||
elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
|
if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
|
||||||
dl.append(XgmiiCtrl.SIG_OS)
|
dl.append(XgmiiCtrl.SEQ_OS)
|
||||||
else:
|
elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
|
||||||
dl.append(XgmiiCtrl.ERROR)
|
dl.append(XgmiiCtrl.SIG_OS)
|
||||||
cl.append(1)
|
|
||||||
dl += data[5:]
|
|
||||||
cl += [0]*3
|
|
||||||
elif data[0] == BaseRBlockType.START_4:
|
|
||||||
# D7 D6 D5 C3 C2 C1 C0 BT
|
|
||||||
dl = ctrl[0:4]
|
|
||||||
cl = [1]*4
|
|
||||||
dl.append(XgmiiCtrl.START)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[5:]
|
|
||||||
cl += [0]*3
|
|
||||||
elif data[0] == BaseRBlockType.OS_START:
|
|
||||||
# D7 D6 D5 O0 D3 D2 D1 BT
|
|
||||||
if data[4] & 0xf == BaseRO.SEQ_OS:
|
|
||||||
dl.append(XgmiiCtrl.SEQ_OS)
|
|
||||||
elif data[4] & 0xf == BaseRO.SIG_OS:
|
|
||||||
dl.append(XgmiiCtrl.SIG_OS)
|
|
||||||
else:
|
|
||||||
dl.append(XgmiiCtrl.ERROR)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[1:4]
|
|
||||||
cl += [0]*3
|
|
||||||
dl.append(XgmiiCtrl.START)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[5:]
|
|
||||||
cl += [0]*3
|
|
||||||
elif data[0] == BaseRBlockType.OS_04:
|
|
||||||
# D7 D6 D5 O4 O0 D3 D2 D1 BT
|
|
||||||
if data[4] & 0xf == BaseRO.SEQ_OS:
|
|
||||||
dl.append(XgmiiCtrl.SEQ_OS)
|
|
||||||
elif data[4] & 0xf == BaseRO.SIG_OS:
|
|
||||||
dl.append(XgmiiCtrl.SIG_OS)
|
|
||||||
else:
|
|
||||||
dl.append(XgmiiCtrl.ERROR)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[1:4]
|
|
||||||
cl += [0]*3
|
|
||||||
if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
|
|
||||||
dl.append(XgmiiCtrl.SEQ_OS)
|
|
||||||
elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
|
|
||||||
dl.append(XgmiiCtrl.SIG_OS)
|
|
||||||
else:
|
|
||||||
dl.append(XgmiiCtrl.ERROR)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[5:]
|
|
||||||
cl += [0]*3
|
|
||||||
elif data[0] == BaseRBlockType.START_0:
|
|
||||||
# D7 D6 D5 D4 D3 D2 D1 BT
|
|
||||||
dl.append(XgmiiCtrl.START)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[1:]
|
|
||||||
cl += [0]*7
|
|
||||||
elif data[0] == BaseRBlockType.OS_0:
|
|
||||||
# C7 C6 C5 C4 O0 D3 D2 D1 BT
|
|
||||||
if data[4] & 0xf == BaseRO.SEQ_OS:
|
|
||||||
dl.append(XgmiiCtrl.SEQ_OS)
|
|
||||||
elif data[4] & 0xf == BaseRO.SIG_OS:
|
|
||||||
dl.append(XgmiiCtrl.SEQ_OS)
|
|
||||||
else:
|
|
||||||
dl.append(XgmiiCtrl.ERROR)
|
|
||||||
cl.append(1)
|
|
||||||
dl += data[1:4]
|
|
||||||
cl += [0]*3
|
|
||||||
dl += ctrl[4:]
|
|
||||||
cl += [1]*4
|
|
||||||
elif data[0] in {BaseRBlockType.TERM_0, BaseRBlockType.TERM_1,
|
|
||||||
BaseRBlockType.TERM_2, BaseRBlockType.TERM_3, BaseRBlockType.TERM_4,
|
|
||||||
BaseRBlockType.TERM_5, BaseRBlockType.TERM_6, BaseRBlockType.TERM_7}:
|
|
||||||
# C7 C6 C5 C4 C3 C2 C1 BT
|
|
||||||
# C7 C6 C5 C4 C3 C2 D0 BT
|
|
||||||
# C7 C6 C5 C4 C3 D1 D0 BT
|
|
||||||
# C7 C6 C5 C4 D2 D1 D0 BT
|
|
||||||
# C7 C6 C5 D3 D2 D1 D0 BT
|
|
||||||
# C7 C6 D4 D3 D2 D1 D0 BT
|
|
||||||
# C7 D5 D4 D3 D2 D1 D0 BT
|
|
||||||
# D6 D5 D4 D3 D2 D1 D0 BT
|
|
||||||
term_lane = block_type_term_lane_mapping[data[0]]
|
|
||||||
dl += data[1:term_lane+1]
|
|
||||||
cl += [0]*term_lane
|
|
||||||
dl.append(XgmiiCtrl.TERM)
|
|
||||||
cl.append(1)
|
|
||||||
dl += ctrl[term_lane+1:]
|
|
||||||
cl += [1]*(7-term_lane)
|
|
||||||
else:
|
else:
|
||||||
# invalid block type
|
dl.append(XgmiiCtrl.ERROR)
|
||||||
self.log.warning("Invalid block type")
|
cl.append(1)
|
||||||
dl = [XgmiiCtrl.ERROR]*8
|
dl += data[5:]
|
||||||
cl = [1]*8
|
cl += [0]*3
|
||||||
|
elif data[0] == BaseRBlockType.START_4:
|
||||||
|
# D7 D6 D5 C3 C2 C1 C0 BT
|
||||||
|
dl = ctrl[0:4]
|
||||||
|
cl = [1]*4
|
||||||
|
dl.append(XgmiiCtrl.START)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[5:]
|
||||||
|
cl += [0]*3
|
||||||
|
elif data[0] == BaseRBlockType.OS_START:
|
||||||
|
# D7 D6 D5 O0 D3 D2 D1 BT
|
||||||
|
if data[4] & 0xf == BaseRO.SEQ_OS:
|
||||||
|
dl.append(XgmiiCtrl.SEQ_OS)
|
||||||
|
elif data[4] & 0xf == BaseRO.SIG_OS:
|
||||||
|
dl.append(XgmiiCtrl.SIG_OS)
|
||||||
|
else:
|
||||||
|
dl.append(XgmiiCtrl.ERROR)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[1:4]
|
||||||
|
cl += [0]*3
|
||||||
|
dl.append(XgmiiCtrl.START)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[5:]
|
||||||
|
cl += [0]*3
|
||||||
|
elif data[0] == BaseRBlockType.OS_04:
|
||||||
|
# D7 D6 D5 O4 O0 D3 D2 D1 BT
|
||||||
|
if data[4] & 0xf == BaseRO.SEQ_OS:
|
||||||
|
dl.append(XgmiiCtrl.SEQ_OS)
|
||||||
|
elif data[4] & 0xf == BaseRO.SIG_OS:
|
||||||
|
dl.append(XgmiiCtrl.SIG_OS)
|
||||||
|
else:
|
||||||
|
dl.append(XgmiiCtrl.ERROR)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[1:4]
|
||||||
|
cl += [0]*3
|
||||||
|
if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
|
||||||
|
dl.append(XgmiiCtrl.SEQ_OS)
|
||||||
|
elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
|
||||||
|
dl.append(XgmiiCtrl.SIG_OS)
|
||||||
|
else:
|
||||||
|
dl.append(XgmiiCtrl.ERROR)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[5:]
|
||||||
|
cl += [0]*3
|
||||||
|
elif data[0] == BaseRBlockType.START_0:
|
||||||
|
# D7 D6 D5 D4 D3 D2 D1 BT
|
||||||
|
dl.append(XgmiiCtrl.START)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[1:]
|
||||||
|
cl += [0]*7
|
||||||
|
elif data[0] == BaseRBlockType.OS_0:
|
||||||
|
# C7 C6 C5 C4 O0 D3 D2 D1 BT
|
||||||
|
if data[4] & 0xf == BaseRO.SEQ_OS:
|
||||||
|
dl.append(XgmiiCtrl.SEQ_OS)
|
||||||
|
elif data[4] & 0xf == BaseRO.SIG_OS:
|
||||||
|
dl.append(XgmiiCtrl.SEQ_OS)
|
||||||
|
else:
|
||||||
|
dl.append(XgmiiCtrl.ERROR)
|
||||||
|
cl.append(1)
|
||||||
|
dl += data[1:4]
|
||||||
|
cl += [0]*3
|
||||||
|
dl += ctrl[4:]
|
||||||
|
cl += [1]*4
|
||||||
|
elif data[0] in {BaseRBlockType.TERM_0, BaseRBlockType.TERM_1,
|
||||||
|
BaseRBlockType.TERM_2, BaseRBlockType.TERM_3, BaseRBlockType.TERM_4,
|
||||||
|
BaseRBlockType.TERM_5, BaseRBlockType.TERM_6, BaseRBlockType.TERM_7}:
|
||||||
|
# C7 C6 C5 C4 C3 C2 C1 BT
|
||||||
|
# C7 C6 C5 C4 C3 C2 D0 BT
|
||||||
|
# C7 C6 C5 C4 C3 D1 D0 BT
|
||||||
|
# C7 C6 C5 C4 D2 D1 D0 BT
|
||||||
|
# C7 C6 C5 D3 D2 D1 D0 BT
|
||||||
|
# C7 C6 D4 D3 D2 D1 D0 BT
|
||||||
|
# C7 D5 D4 D3 D2 D1 D0 BT
|
||||||
|
# D6 D5 D4 D3 D2 D1 D0 BT
|
||||||
|
term_lane = block_type_term_lane_mapping[data[0]]
|
||||||
|
dl += data[1:term_lane+1]
|
||||||
|
cl += [0]*term_lane
|
||||||
|
dl.append(XgmiiCtrl.TERM)
|
||||||
|
cl.append(1)
|
||||||
|
dl += ctrl[term_lane+1:]
|
||||||
|
cl += [1]*(7-term_lane)
|
||||||
else:
|
else:
|
||||||
# invalid sync header
|
# invalid block type
|
||||||
self.log.warning("Invalid sync header")
|
self.log.warning("Invalid block type")
|
||||||
dl = [XgmiiCtrl.ERROR]*8
|
dl = [XgmiiCtrl.ERROR]*8
|
||||||
cl = [1]*8
|
cl = [1]*8
|
||||||
|
else:
|
||||||
|
# invalid sync header
|
||||||
|
self.log.warning("Invalid sync header")
|
||||||
|
dl = [XgmiiCtrl.ERROR]*8
|
||||||
|
cl = [1]*8
|
||||||
|
|
||||||
for offset in range(self.byte_lanes):
|
for offset in range(self.byte_lanes):
|
||||||
d_val = dl[offset]
|
d_val = dl[offset]
|
||||||
c_val = cl[offset]
|
c_val = cl[offset]
|
||||||
|
|
||||||
if frame is None:
|
|
||||||
if c_val and d_val == XgmiiCtrl.START:
|
|
||||||
# start
|
|
||||||
frame = XgmiiFrame(bytearray([EthPre.PRE]), [0])
|
|
||||||
frame.sim_time_start = get_sim_time()
|
|
||||||
frame.start_lane = offset
|
|
||||||
else:
|
|
||||||
if c_val:
|
|
||||||
# got a control character; terminate frame reception
|
|
||||||
if d_val != XgmiiCtrl.TERM:
|
|
||||||
# store control character if it's not a termination
|
|
||||||
frame.data.append(d_val)
|
|
||||||
frame.ctrl.append(c_val)
|
|
||||||
|
|
||||||
frame.compact()
|
|
||||||
frame.sim_time_end = get_sim_time()
|
|
||||||
self.log.info("RX frame: %s", frame)
|
|
||||||
|
|
||||||
self.queue_occupancy_bytes += len(frame)
|
|
||||||
self.queue_occupancy_frames += 1
|
|
||||||
|
|
||||||
self.queue.put_nowait(frame)
|
|
||||||
self.active_event.set()
|
|
||||||
|
|
||||||
frame = None
|
|
||||||
else:
|
|
||||||
if frame.sim_time_sfd is None and d_val == EthPre.SFD:
|
|
||||||
frame.sim_time_sfd = get_sim_time()
|
|
||||||
|
|
||||||
|
if frame is None:
|
||||||
|
if c_val and d_val == XgmiiCtrl.START:
|
||||||
|
# start
|
||||||
|
frame = XgmiiFrame(bytearray([EthPre.PRE]), [0])
|
||||||
|
frame.sim_time_start = get_sim_time()
|
||||||
|
frame.start_lane = offset
|
||||||
|
else:
|
||||||
|
if c_val:
|
||||||
|
# got a control character; terminate frame reception
|
||||||
|
if d_val != XgmiiCtrl.TERM:
|
||||||
|
# store control character if it's not a termination
|
||||||
frame.data.append(d_val)
|
frame.data.append(d_val)
|
||||||
frame.ctrl.append(c_val)
|
frame.ctrl.append(c_val)
|
||||||
|
|
||||||
|
frame.compact()
|
||||||
|
frame.sim_time_end = get_sim_time()
|
||||||
|
self.log.info("RX frame: %s", frame)
|
||||||
|
|
||||||
|
self.queue_occupancy_bytes += len(frame)
|
||||||
|
self.queue_occupancy_frames += 1
|
||||||
|
|
||||||
|
self.queue.put_nowait(frame)
|
||||||
|
self.active_event.set()
|
||||||
|
|
||||||
|
frame = None
|
||||||
|
else:
|
||||||
|
if frame.sim_time_sfd is None and d_val == EthPre.SFD:
|
||||||
|
frame.sim_time_sfd = get_sim_time()
|
||||||
|
|
||||||
|
frame.data.append(d_val)
|
||||||
|
frame.ctrl.append(c_val)
|
||||||
|
|||||||
Reference in New Issue
Block a user