From ab01a1ba42d74f83f6f723610ea8867e4820a9f2 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 16 Feb 2026 12:34:28 -0800 Subject: [PATCH] cndm: Clean up ports Signed-off-by: Alex Forencich --- src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv | 122 ++++++++-------- src/cndm/rtl/cndm_micro_pcie_us.sv | 130 +++++++++--------- 2 files changed, 126 insertions(+), 126 deletions(-) diff --git a/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv b/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv index 9d94853..8c5658d 100644 --- a/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv +++ b/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv @@ -36,84 +36,84 @@ module fpga_core # * Clock: 125MHz * Synchronous reset */ - input wire logic clk_125mhz, - input wire logic rst_125mhz, + input wire logic clk_125mhz, + input wire logic rst_125mhz, /* * GPIO */ - output wire logic sfp_led[2], - output wire logic [3:0] led, - output wire logic led_r, - output wire logic led_g, - output wire logic led_hb, + output wire logic sfp_led[2], + output wire logic [3:0] led, + output wire logic led_r, + output wire logic led_g, + output wire logic led_hb, /* * Ethernet: SFP+ */ - input wire logic sfp_rx_p[2], - input wire logic sfp_rx_n[2], - output wire logic sfp_tx_p[2], - output wire logic sfp_tx_n[2], - input wire logic sfp_mgt_refclk_p, - input wire logic sfp_mgt_refclk_n, - output wire logic sfp_mgt_refclk_out, - input wire logic [1:0] sfp_npres, - input wire logic [1:0] sfp_tx_fault, - input wire logic [1:0] sfp_los, + input wire logic sfp_rx_p[2], + input wire logic sfp_rx_n[2], + output wire logic sfp_tx_p[2], + output wire logic sfp_tx_n[2], + input wire logic sfp_mgt_refclk_p, + input wire logic sfp_mgt_refclk_n, + output wire logic sfp_mgt_refclk_out, + input wire logic [1:0] sfp_npres, + input wire logic [1:0] sfp_tx_fault, + input wire logic [1:0] sfp_los, /* * PCIe */ - input wire logic pcie_clk, - input wire logic pcie_rst, - taxi_axis_if.snk s_axis_pcie_cq, - taxi_axis_if.src m_axis_pcie_cc, - taxi_axis_if.src m_axis_pcie_rq, - taxi_axis_if.snk s_axis_pcie_rc, + input wire logic pcie_clk, + input wire logic pcie_rst, + taxi_axis_if.snk s_axis_pcie_cq, + taxi_axis_if.src m_axis_pcie_cc, + taxi_axis_if.src m_axis_pcie_rq, + taxi_axis_if.snk s_axis_pcie_rc, - input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0, - input wire pcie_rq_seq_num_vld0, - input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1, - input wire pcie_rq_seq_num_vld1, + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0, + input wire logic pcie_rq_seq_num_vld0, + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1, + input wire logic pcie_rq_seq_num_vld1, - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, + input wire logic [2:0] cfg_max_payload, + input wire logic [2:0] cfg_max_read_req, + input wire logic [3:0] cfg_rcb_status, - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - output wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, + output wire logic [9:0] cfg_mgmt_addr, + output wire logic [7:0] cfg_mgmt_function_number, + output wire logic cfg_mgmt_write, + output wire logic [31:0] cfg_mgmt_write_data, + output wire logic [3:0] cfg_mgmt_byte_enable, + output wire logic cfg_mgmt_read, + output wire logic [31:0] cfg_mgmt_read_data, + input wire logic cfg_mgmt_read_write_done, - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, + input wire logic [7:0] cfg_fc_ph, + input wire logic [11:0] cfg_fc_pd, + input wire logic [7:0] cfg_fc_nph, + input wire logic [11:0] cfg_fc_npd, + input wire logic [7:0] cfg_fc_cplh, + input wire logic [11:0] cfg_fc_cpld, + output wire logic [2:0] cfg_fc_sel, - input wire [3:0] cfg_interrupt_msi_enable, - input wire [11:0] cfg_interrupt_msi_mmenable, - input wire cfg_interrupt_msi_mask_update, - input wire [31:0] cfg_interrupt_msi_data, - output wire [1:0] cfg_interrupt_msi_select, - output wire [31:0] cfg_interrupt_msi_int, - output wire [31:0] cfg_interrupt_msi_pending_status, - output wire cfg_interrupt_msi_pending_status_data_enable, - output wire [1:0] cfg_interrupt_msi_pending_status_function_num, - input wire cfg_interrupt_msi_sent, - input wire cfg_interrupt_msi_fail, - output wire [2:0] cfg_interrupt_msi_attr, - output wire cfg_interrupt_msi_tph_present, - output wire [1:0] cfg_interrupt_msi_tph_type, - output wire [7:0] cfg_interrupt_msi_tph_st_tag, - output wire [7:0] cfg_interrupt_msi_function_number + input wire logic [3:0] cfg_interrupt_msi_enable, + input wire logic [11:0] cfg_interrupt_msi_mmenable, + input wire logic cfg_interrupt_msi_mask_update, + input wire logic [31:0] cfg_interrupt_msi_data, + output wire logic [1:0] cfg_interrupt_msi_select, + output wire logic [31:0] cfg_interrupt_msi_int, + output wire logic [31:0] cfg_interrupt_msi_pending_status, + output wire logic cfg_interrupt_msi_pending_status_data_enable, + output wire logic [1:0] cfg_interrupt_msi_pending_status_function_num, + input wire logic cfg_interrupt_msi_sent, + input wire logic cfg_interrupt_msi_fail, + output wire logic [2:0] cfg_interrupt_msi_attr, + output wire logic cfg_interrupt_msi_tph_present, + output wire logic [1:0] cfg_interrupt_msi_tph_type, + output wire logic [7:0] cfg_interrupt_msi_tph_st_tag, + output wire logic [7:0] cfg_interrupt_msi_function_number ); localparam logic PTP_TS_FMT_TOD = 1'b0; diff --git a/src/cndm/rtl/cndm_micro_pcie_us.sv b/src/cndm/rtl/cndm_micro_pcie_us.sv index cad06c7..a145e43 100644 --- a/src/cndm/rtl/cndm_micro_pcie_us.sv +++ b/src/cndm/rtl/cndm_micro_pcie_us.sv @@ -34,85 +34,85 @@ module cndm_micro_pcie_us #( /* * PCIe */ - input wire logic pcie_clk, - input wire logic pcie_rst, - taxi_axis_if.snk s_axis_pcie_cq, - taxi_axis_if.src m_axis_pcie_cc, - taxi_axis_if.src m_axis_pcie_rq, - taxi_axis_if.snk s_axis_pcie_rc, + input wire logic pcie_clk, + input wire logic pcie_rst, + taxi_axis_if.snk s_axis_pcie_cq, + taxi_axis_if.src m_axis_pcie_cc, + taxi_axis_if.src m_axis_pcie_rq, + taxi_axis_if.snk s_axis_pcie_rc, - input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0, - input wire pcie_rq_seq_num_vld0, - input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1, - input wire pcie_rq_seq_num_vld1, + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0, + input wire logic pcie_rq_seq_num_vld0, + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1, + input wire logic pcie_rq_seq_num_vld1, - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, + input wire logic [2:0] cfg_max_payload, + input wire logic [2:0] cfg_max_read_req, + input wire logic [3:0] cfg_rcb_status, - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, + output wire logic [9:0] cfg_mgmt_addr, + output wire logic [7:0] cfg_mgmt_function_number, + output wire logic cfg_mgmt_write, + output wire logic [31:0] cfg_mgmt_write_data, + output wire logic [3:0] cfg_mgmt_byte_enable, + output wire logic cfg_mgmt_read, + input wire logic [31:0] cfg_mgmt_read_data, + input wire logic cfg_mgmt_read_write_done, - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, + input wire logic [7:0] cfg_fc_ph, + input wire logic [11:0] cfg_fc_pd, + input wire logic [7:0] cfg_fc_nph, + input wire logic [11:0] cfg_fc_npd, + input wire logic [7:0] cfg_fc_cplh, + input wire logic [11:0] cfg_fc_cpld, + output wire logic [2:0] cfg_fc_sel, - input wire [3:0] cfg_interrupt_msi_enable, - input wire [11:0] cfg_interrupt_msi_mmenable, - input wire cfg_interrupt_msi_mask_update, - input wire [31:0] cfg_interrupt_msi_data, - output wire [1:0] cfg_interrupt_msi_select, - output wire [31:0] cfg_interrupt_msi_int, - output wire [31:0] cfg_interrupt_msi_pending_status, - output wire cfg_interrupt_msi_pending_status_data_enable, - output wire [1:0] cfg_interrupt_msi_pending_status_function_num, - input wire cfg_interrupt_msi_sent, - input wire cfg_interrupt_msi_fail, - output wire [2:0] cfg_interrupt_msi_attr, - output wire cfg_interrupt_msi_tph_present, - output wire [1:0] cfg_interrupt_msi_tph_type, - output wire [7:0] cfg_interrupt_msi_tph_st_tag, - output wire [7:0] cfg_interrupt_msi_function_number, + input wire logic [3:0] cfg_interrupt_msi_enable, + input wire logic [11:0] cfg_interrupt_msi_mmenable, + input wire logic cfg_interrupt_msi_mask_update, + input wire logic [31:0] cfg_interrupt_msi_data, + output wire logic [1:0] cfg_interrupt_msi_select, + output wire logic [31:0] cfg_interrupt_msi_int, + output wire logic [31:0] cfg_interrupt_msi_pending_status, + output wire logic cfg_interrupt_msi_pending_status_data_enable, + output wire logic [1:0] cfg_interrupt_msi_pending_status_function_num, + input wire logic cfg_interrupt_msi_sent, + input wire logic cfg_interrupt_msi_fail, + output wire logic [2:0] cfg_interrupt_msi_attr, + output wire logic cfg_interrupt_msi_tph_present, + output wire logic [1:0] cfg_interrupt_msi_tph_type, + output wire logic [7:0] cfg_interrupt_msi_tph_st_tag, + output wire logic [7:0] cfg_interrupt_msi_function_number, /* * PTP */ - input wire logic ptp_clk = 1'b0, - input wire logic ptp_rst = 1'b0, - input wire logic ptp_sample_clk = 1'b0, - input wire logic ptp_td_sdi = 1'b0, - output wire logic ptp_td_sdo, - output wire logic ptp_pps, - output wire logic ptp_pps_str, - output wire logic ptp_sync_locked, - output wire logic [63:0] ptp_sync_ts_rel, - output wire logic ptp_sync_ts_rel_step, - output wire logic [95:0] ptp_sync_ts_tod, - output wire logic ptp_sync_ts_tod_step, - output wire logic ptp_sync_pps, - output wire logic ptp_sync_pps_str, + input wire logic ptp_clk = 1'b0, + input wire logic ptp_rst = 1'b0, + input wire logic ptp_sample_clk = 1'b0, + input wire logic ptp_td_sdi = 1'b0, + output wire logic ptp_td_sdo, + output wire logic ptp_pps, + output wire logic ptp_pps_str, + output wire logic ptp_sync_locked, + output wire logic [63:0] ptp_sync_ts_rel, + output wire logic ptp_sync_ts_rel_step, + output wire logic [95:0] ptp_sync_ts_tod, + output wire logic ptp_sync_ts_tod_step, + output wire logic ptp_sync_pps, + output wire logic ptp_sync_pps_str, /* * Ethernet */ - input wire logic mac_tx_clk[PORTS], - input wire logic mac_tx_rst[PORTS], - taxi_axis_if.src mac_axis_tx[PORTS], - taxi_axis_if.snk mac_axis_tx_cpl[PORTS], + input wire logic mac_tx_clk[PORTS], + input wire logic mac_tx_rst[PORTS], + taxi_axis_if.src mac_axis_tx[PORTS], + taxi_axis_if.snk mac_axis_tx_cpl[PORTS], - input wire logic mac_rx_clk[PORTS], - input wire logic mac_rx_rst[PORTS], - taxi_axis_if.snk mac_axis_rx[PORTS] + input wire logic mac_rx_clk[PORTS], + input wire logic mac_rx_rst[PORTS], + taxi_axis_if.snk mac_axis_rx[PORTS] ); localparam CL_PORTS = $clog2(PORTS);