axi: Use SV enums in AXI components

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/axi/rtl/taxi_axi_adapter_rd.sv

@@ -115,13 +115,14 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_DATA_READ = 2'd2,
-        STATE_DATA_SPLIT = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_DATA_READ,
+        STATE_DATA_SPLIT
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;
@@ -480,11 +481,12 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;

src/axi/rtl/taxi_axi_adapter_wr.sv

@@ -122,13 +122,14 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_DATA_2 = 2'd2,
-        STATE_RESP = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_DATA_2,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;
@@ -505,13 +506,14 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_DATA_2 = 2'd2,
-        STATE_RESP = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_DATA_2,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;

src/axi/rtl/taxi_axi_axil_adapter_rd.sv

@@ -89,11 +89,12 @@ if (AXIL_BYTE_LANES == AXI_BYTE_LANES) begin : translate
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [AXI_ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;
@@ -251,13 +252,14 @@ end else if (AXIL_BYTE_LANES > AXI_BYTE_LANES) begin : upsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_DATA_READ = 2'd2,
-        STATE_DATA_SPLIT = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_DATA_READ,
+        STATE_DATA_SPLIT
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [AXI_ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;
@@ -483,11 +485,12 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [AXI_ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;

src/axi/rtl/taxi_axi_axil_adapter_wr.sv

@@ -91,12 +91,13 @@ if (AXIL_BYTE_LANES == AXI_BYTE_LANES) begin : translate
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_RESP = 2'd2;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [AXI_ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;
@@ -295,13 +296,14 @@ end else if (AXIL_BYTE_LANES > AXI_BYTE_LANES) begin : upsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_DATA_2 = 2'd2,
-        STATE_RESP = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_DATA_2,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [AXI_ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;
@@ -547,13 +549,14 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_DATA_2 = 2'd2,
-        STATE_RESP = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_DATA_2,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [AXI_ID_W-1:0] id_reg = '0, id_next;
     logic [ADDR_W-1:0] addr_reg = '0, addr_next;

src/axi/rtl/taxi_axi_crossbar_addr.sv

@@ -213,11 +213,12 @@ initial begin
     end
 end
 
-localparam logic [0:0]
-    STATE_IDLE = 1'd0,
-    STATE_DECODE = 1'd1;
+typedef enum logic [0:0] {
+    STATE_IDLE,
+    STATE_DECODE
+} state_t;
 
-logic [0:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic s_axi_aready_reg = 1'b0, s_axi_aready_next;
 

src/axi/rtl/taxi_axi_fifo_rd.sv

@@ -100,11 +100,12 @@ if (FIFO_DELAY) begin
 
     localparam COUNT_W = (FIFO_AW > 8 ? FIFO_AW : 8) + 1;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_WAIT = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_WAIT
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [COUNT_W-1:0] count_reg = 0, count_next;
 

src/axi/rtl/taxi_axi_fifo_wr.sv

@@ -99,12 +99,13 @@ if (WUSER_EN) assign s_axi_w[WUSER_OFFSET +: WUSER_W] = s_axi_wr.wuser;
 if (FIFO_DELAY) begin
     // store AW channel value until W channel burst is stored in FIFO or FIFO is full
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_TRANSFER_IN = 2'd1,
-        STATE_TRANSFER_OUT = 2'd2;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_TRANSFER_IN,
+        STATE_TRANSFER_OUT
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic hold_reg = 1'b1, hold_next;
     logic [8:0] count_reg = 9'd0, count_next;

src/axi/rtl/taxi_axi_interconnect_rd.sv

@@ -182,14 +182,15 @@ initial begin
     end
 end
 
-localparam logic [2:0]
-    STATE_IDLE = 3'd0,
-    STATE_DECODE = 3'd1,
-    STATE_READ = 3'd2,
-    STATE_READ_DROP = 3'd3,
-    STATE_WAIT_IDLE = 3'd4;
+typedef enum logic [2:0] {
+    STATE_IDLE,
+    STATE_DECODE,
+    STATE_READ,
+    STATE_READ_DROP,
+    STATE_WAIT_IDLE
+} state_t;
 
-logic [2:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic match;
 

src/axi/rtl/taxi_axi_interconnect_wr.sv

@@ -186,15 +186,16 @@ initial begin
     end
 end
 
-localparam logic [2:0]
-    STATE_IDLE = 3'd0,
-    STATE_DECODE = 3'd1,
-    STATE_WRITE = 3'd2,
-    STATE_WRITE_RESP = 3'd3,
-    STATE_WRITE_DROP = 3'd4,
-    STATE_WAIT_IDLE = 3'd5;
+typedef enum logic [2:0] {
+    STATE_IDLE,
+    STATE_DECODE,
+    STATE_WRITE,
+    STATE_WRITE_RESP,
+    STATE_WRITE_DROP,
+    STATE_WAIT_IDLE
+} state_t;
 
-logic [2:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic match;
 

src/axi/rtl/taxi_axi_ram.sv

@@ -56,18 +56,20 @@ if (s_axi_wr.DATA_W != s_axi_rd.DATA_W)
 if (s_axi_wr.ADDR_W < ADDR_W || s_axi_rd.ADDR_W < ADDR_W)
     $fatal(0, "Error: AXI address width is insufficient (instance %m)");
 
-localparam [0:0]
-    READ_STATE_IDLE = 1'd0,
-    READ_STATE_BURST = 1'd1;
+typedef enum logic [0:0] {
+    READ_STATE_IDLE,
+    READ_STATE_BURST
+} read_state_t;
 
-logic [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
+read_state_t read_state_reg = READ_STATE_IDLE, read_state_next;
 
-localparam [1:0]
-    WRITE_STATE_IDLE = 2'd0,
-    WRITE_STATE_BURST = 2'd1,
-    WRITE_STATE_RESP = 2'd2;
+typedef enum logic [1:0] {
+    WRITE_STATE_IDLE,
+    WRITE_STATE_BURST,
+    WRITE_STATE_RESP
+} write_state_t;
 
-logic [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;
+write_state_t write_state_reg = WRITE_STATE_IDLE, write_state_next;
 
 logic mem_wr_en;
 logic mem_rd_en;

src/axi/rtl/taxi_axil_adapter_rd.sv

@@ -86,11 +86,12 @@ if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
 end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
     // output is wider; upsize
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
     logic [S_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
@@ -203,11 +204,12 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next;
 

src/axi/rtl/taxi_axil_adapter_wr.sv

@@ -93,11 +93,12 @@ if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
 end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
     // output is wider; upsize
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
     logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
@@ -220,12 +221,13 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_RESP = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [DATA_W-1:0] data_reg = '0, data_next;
     logic [STRB_W-1:0] strb_reg = '0, strb_next;

src/axi/rtl/taxi_axil_apb_adapter.sv

@@ -96,11 +96,12 @@ localparam [1:0]
 if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
     // same width; translate
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic last_read_reg = 1'b0, last_read_next;
 
@@ -294,11 +295,12 @@ if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
 end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
     // output is wider; upsize
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic last_read_reg = 1'b0, last_read_next;
 
@@ -503,11 +505,12 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic last_read_reg = 1'b0, last_read_next;
 

src/axi/rtl/taxi_axil_axi_adapter_rd.sv

@@ -95,11 +95,12 @@ if (AXI_BYTE_LANES == AXIL_BYTE_LANES) begin : bypass
 end else if (AXI_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
     // output is wider; upsize
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
     logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
@@ -220,11 +221,12 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next;
 

src/axi/rtl/taxi_axil_axi_adapter_wr.sv

@@ -103,11 +103,12 @@ if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
 end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
     // output is wider; upsize
 
-    localparam [0:0]
-        STATE_IDLE = 1'd0,
-        STATE_DATA = 1'd1;
+    typedef enum logic [0:0] {
+        STATE_IDLE,
+        STATE_DATA
+    } state_t;
 
-    logic [0:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
     logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
@@ -239,12 +240,13 @@ end else begin : downsize
     localparam SEG_DATA_W = DATA_W / SEG_COUNT;
     localparam SEG_STRB_W = STRB_W / SEG_COUNT;
 
-    localparam [1:0]
-        STATE_IDLE = 2'd0,
-        STATE_DATA = 2'd1,
-        STATE_RESP = 2'd3;
+    typedef enum logic [1:0] {
+        STATE_IDLE,
+        STATE_DATA,
+        STATE_RESP
+    } state_t;
 
-    logic [1:0] state_reg = STATE_IDLE, state_next;
+    state_t state_reg = STATE_IDLE, state_next;
 
     logic [DATA_W-1:0] data_reg = '0, data_next;
     logic [STRB_W-1:0] strb_reg = '0, strb_next;

src/axi/rtl/taxi_axil_crossbar_addr.sv

@@ -189,11 +189,12 @@ initial begin
     end
 end
 
-localparam logic [0:0]
-    STATE_IDLE = 1'd0,
-    STATE_DECODE = 1'd1;
+typedef enum logic [0:0] {
+    STATE_IDLE,
+    STATE_DECODE
+} state_t;
 
-logic [0:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic s_axil_aready_reg = 1'b0, s_axil_aready_next;
 

src/axi/rtl/taxi_axil_interconnect_rd.sv

@@ -177,13 +177,14 @@ initial begin
     end
 end
 
-localparam logic [1:0]
-    STATE_IDLE = 2'd0,
-    STATE_DECODE = 2'd1,
-    STATE_READ = 2'd2,
-    STATE_WAIT_IDLE = 2'd3;
+typedef enum logic [1:0] {
+    STATE_IDLE,
+    STATE_DECODE,
+    STATE_READ,
+    STATE_WAIT_IDLE
+} state_t;
 
-logic [1:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic match;
 

src/axi/rtl/taxi_axil_interconnect_wr.sv

@@ -179,15 +179,16 @@ initial begin
     end
 end
 
-localparam logic [2:0]
-    STATE_IDLE = 3'd0,
-    STATE_DECODE = 3'd1,
-    STATE_WRITE = 3'd2,
-    STATE_WRITE_RESP = 3'd3,
-    STATE_WRITE_DROP = 3'd4,
-    STATE_WAIT_IDLE = 3'd5;
+typedef enum logic [2:0] {
+    STATE_IDLE,
+    STATE_DECODE,
+    STATE_WRITE,
+    STATE_WRITE_RESP,
+    STATE_WRITE_DROP,
+    STATE_WAIT_IDLE
+} state_t;
 
-logic [2:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic match;