diff --git a/README.md b/README.md index ef4d731..1c1478b 100644 --- a/README.md +++ b/README.md @@ -27,6 +27,7 @@ To facilitate the dual-license model, contributions to the project can only be a * APB * SV interface for APB * Interconnect + * Width converter * Single-port RAM * Dual-port RAM * AXI diff --git a/src/apb/rtl/taxi_apb_adapter.sv b/src/apb/rtl/taxi_apb_adapter.sv new file mode 100644 index 0000000..5bfbf92 --- /dev/null +++ b/src/apb/rtl/taxi_apb_adapter.sv @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * APB width adapter + */ +module taxi_apb_adapter +( + input wire logic clk, + input wire logic rst, + + /* + * APB slave interface + */ + taxi_apb_if.slv s_apb, + + /* + * APB master interface + */ + taxi_apb_if.mst m_apb +); + +// extract parameters +localparam S_DATA_W = s_apb.DATA_W; +localparam ADDR_W = s_apb.ADDR_W; +localparam S_STRB_W = s_apb.STRB_W; +localparam logic PAUSER_EN = s_apb.PAUSER_EN && m_apb.PAUSER_EN; +localparam PAUSER_W = s_apb.PAUSER_W; +localparam logic PWUSER_EN = s_apb.PWUSER_EN && m_apb.PWUSER_EN; +localparam PWUSER_W = s_apb.PWUSER_W; +localparam logic PRUSER_EN = s_apb.PRUSER_EN && m_apb.PRUSER_EN; +localparam PRUSER_W = s_apb.PRUSER_W; +localparam logic PBUSER_EN = s_apb.PBUSER_EN && m_apb.PBUSER_EN; +localparam PBUSER_W = s_apb.PBUSER_W; + +localparam M_DATA_W = m_apb.DATA_W; +localparam M_STRB_W = m_apb.STRB_W; + +localparam S_ADDR_BIT_OFFSET = $clog2(S_STRB_W); +localparam M_ADDR_BIT_OFFSET = $clog2(M_STRB_W); +localparam S_BYTE_LANES = S_STRB_W; +localparam M_BYTE_LANES = M_STRB_W; +localparam S_BYTE_W = S_DATA_W/S_BYTE_LANES; +localparam M_BYTE_W = M_DATA_W/M_BYTE_LANES; +localparam S_ADDR_MASK = {ADDR_W{1'b1}} << S_ADDR_BIT_OFFSET; +localparam M_ADDR_MASK = {ADDR_W{1'b1}} << M_ADDR_BIT_OFFSET; + +// check configuration +if (S_BYTE_W * S_STRB_W != S_DATA_W) + $fatal(0, "Error: APB slave interface data width not evenly divisible (instance %m)"); + +if (M_BYTE_W * M_STRB_W != M_DATA_W) + $fatal(0, "Error: APB master interface data width not evenly divisible (instance %m)"); + +if (S_BYTE_W != M_BYTE_W) + $fatal(0, "Error: byte size mismatch (instance %m)"); + +if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES) + $fatal(0, "Error: APB slave interface byte lane count must be even power of two (instance %m)"); + +if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES) + $fatal(0, "Error: APB master interface byte lane count must be even power of two (instance %m)"); + +if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass + // same width; bypass + + assign m_apb.paddr = s_apb.paddr; + assign m_apb.pprot = s_apb.pprot; + assign m_apb.psel = s_apb.psel; + assign m_apb.penable = s_apb.penable; + assign m_apb.pwrite = s_apb.pwrite; + assign m_apb.pwdata = s_apb.pwdata; + assign m_apb.pstrb = s_apb.pstrb; + assign s_apb.pready = m_apb.pready; + assign s_apb.prdata = m_apb.prdata; + assign s_apb.pslverr = m_apb.pslverr; + assign m_apb.pauser = PAUSER_EN ? s_apb.pauser : '0; + assign m_apb.pwuser = PWUSER_EN ? s_apb.pwuser : '0; + assign s_apb.pruser = PRUSER_EN ? m_apb.pruser : '0; + assign s_apb.pbuser = PBUSER_EN ? m_apb.pbuser : '0; + +end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize + // output is wider; upsize + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_DATA = 1'd1; + + logic [0:0] state_reg = STATE_IDLE, state_next; + + logic s_apb_pready_reg = 1'b0, s_apb_pready_next; + logic [S_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next; + logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next; + logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next; + logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next; + + logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next; + logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next; + logic m_apb_psel_reg = 1'b0, m_apb_psel_next; + logic m_apb_penable_reg = 1'b0, m_apb_penable_next; + logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next; + logic [M_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next; + logic [M_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next; + logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next; + logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next; + + assign s_apb.pready = s_apb_pready_reg; + assign s_apb.prdata = s_apb_prdata_reg; + assign s_apb.pslverr = s_apb_pslverr_reg; + assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0; + assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0; + + assign m_apb.paddr = m_apb_paddr_reg; + assign m_apb.pprot = m_apb_pprot_reg; + assign m_apb.psel = m_apb_psel_reg; + assign m_apb.penable = m_apb_penable_reg; + assign m_apb.pwrite = m_apb_pwrite_reg; + assign m_apb.pwdata = m_apb_pwdata_reg; + assign m_apb.pstrb = m_apb_pstrb_reg; + assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0; + assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0; + + always_comb begin + state_next = STATE_IDLE; + + s_apb_pready_next = 1'b0; + s_apb_prdata_next = s_apb_prdata_reg; + s_apb_pslverr_next = s_apb_pslverr_reg; + s_apb_pruser_next = s_apb_pruser_reg; + s_apb_pbuser_next = s_apb_pbuser_reg; + + m_apb_paddr_next = m_apb_paddr_reg; + m_apb_pprot_next = m_apb_pprot_reg; + m_apb_psel_next = 1'b0; + m_apb_penable_next = 1'b0; + m_apb_pwrite_next = m_apb_pwrite_reg; + m_apb_pwdata_next = m_apb_pwdata_reg; + m_apb_pstrb_next = m_apb_pstrb_reg; + m_apb_pauser_next = m_apb_pauser_reg; + m_apb_pwuser_next = m_apb_pwuser_reg; + + case (state_reg) + STATE_IDLE: begin + m_apb_paddr_next = s_apb.paddr; + m_apb_pprot_next = s_apb.pprot; + m_apb_pwrite_next = s_apb.pwrite; + m_apb_pwdata_next = {(M_BYTE_LANES/S_BYTE_LANES){s_apb.pwdata}}; + m_apb_pstrb_next = '0; + m_apb_pstrb_next[s_apb.paddr[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_STRB_W +: S_STRB_W] = s_apb.pstrb; + m_apb_pauser_next = s_apb.pauser; + m_apb_pwuser_next = s_apb.pwuser; + + if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + m_apb_psel_next = 1'b1; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_apb_psel_next = 1'b1; + m_apb_penable_next = 1'b1; + + s_apb_pready_next = 1'b0; + s_apb_prdata_next = m_apb.prdata[m_apb_paddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_DATA_W +: S_DATA_W]; + s_apb_pslverr_next = m_apb.pslverr; + s_apb_pruser_next = m_apb.pruser; + s_apb_pbuser_next = m_apb.pbuser; + + if (m_apb.psel && m_apb.penable && m_apb.pready) begin + m_apb_psel_next = 1'b0; + m_apb_penable_next = 1'b0; + s_apb_pready_next = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_DATA; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + s_apb_pready_reg <= s_apb_pready_next; + s_apb_prdata_reg <= s_apb_prdata_next; + s_apb_pslverr_reg <= s_apb_pslverr_next; + s_apb_pruser_reg <= s_apb_pruser_next; + s_apb_pbuser_reg <= s_apb_pbuser_next; + + m_apb_paddr_reg <= m_apb_paddr_next; + m_apb_pprot_reg <= m_apb_pprot_next; + m_apb_psel_reg <= m_apb_psel_next; + m_apb_penable_reg <= m_apb_penable_next; + m_apb_pwrite_reg <= m_apb_pwrite_next; + m_apb_pwdata_reg <= m_apb_pwdata_next; + m_apb_pstrb_reg <= m_apb_pstrb_next; + m_apb_pauser_reg <= m_apb_pauser_next; + m_apb_pwuser_reg <= m_apb_pwuser_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_apb_pready_reg <= 1'b0; + + m_apb_psel_reg <= 1'b0; + m_apb_penable_reg <= 1'b0; + end + end + +end else begin : downsize + // output is narrower; downsize + + // output bus is wider + localparam DATA_W = S_DATA_W; + localparam STRB_W = S_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES; + localparam SEG_COUNT_W = $clog2(SEG_COUNT); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_DATA = 1'd1; + + logic [0:0] state_reg = STATE_IDLE, state_next; + + logic [DATA_W-1:0] data_reg = '0, data_next; + logic [STRB_W-1:0] strb_reg = '0, strb_next; + + logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next; + + logic s_apb_pready_reg = 1'b0, s_apb_pready_next; + logic [S_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next; + logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next; + logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next; + logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next; + + logic [ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next; + logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next; + logic m_apb_psel_reg = 1'b0, m_apb_psel_next; + logic m_apb_penable_reg = 1'b0, m_apb_penable_next; + logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next; + logic [M_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next; + logic [M_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next; + logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next; + logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next; + + assign s_apb.pready = s_apb_pready_reg; + assign s_apb.prdata = s_apb_prdata_reg; + assign s_apb.pslverr = s_apb_pslverr_reg; + assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0; + assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0; + + assign m_apb.paddr = m_apb_paddr_reg; + assign m_apb.pprot = m_apb_pprot_reg; + assign m_apb.psel = m_apb_psel_reg; + assign m_apb.penable = m_apb_penable_reg; + assign m_apb.pwrite = m_apb_pwrite_reg; + assign m_apb.pwdata = m_apb_pwdata_reg; + assign m_apb.pstrb = m_apb_pstrb_reg; + assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0; + assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0; + + always_comb begin + state_next = STATE_IDLE; + + data_next = data_reg; + strb_next = strb_reg; + + current_seg_next = current_seg_reg; + + s_apb_pready_next = 1'b0; + s_apb_prdata_next = s_apb_prdata_reg; + s_apb_pslverr_next = s_apb_pslverr_reg; + s_apb_pruser_next = s_apb_pruser_reg; + s_apb_pbuser_next = s_apb_pbuser_reg; + + m_apb_paddr_next = m_apb_paddr_reg; + m_apb_pprot_next = m_apb_pprot_reg; + m_apb_psel_next = 1'b0; + m_apb_penable_next = 1'b0; + m_apb_pwrite_next = m_apb_pwrite_reg; + m_apb_pwdata_next = m_apb_pwdata_reg; + m_apb_pstrb_next = m_apb_pstrb_reg; + m_apb_pauser_next = m_apb_pauser_reg; + m_apb_pwuser_next = m_apb_pwuser_reg; + + case (state_reg) + STATE_IDLE: begin + current_seg_next = s_apb.paddr[M_ADDR_BIT_OFFSET +: SEG_COUNT_W]; + + m_apb_paddr_next = s_apb.paddr; + m_apb_pprot_next = s_apb.pprot; + m_apb_pwrite_next = s_apb.pwrite; + data_next = s_apb.pwdata; + strb_next = s_apb.pstrb; + m_apb_pwdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W]; + m_apb_pstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W]; + m_apb_pauser_next = s_apb.pauser; + m_apb_pwuser_next = s_apb.pwuser; + + s_apb_pslverr_next = 1'b0; + + if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + m_apb_psel_next = 1'b1; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_apb_psel_next = 1'b1; + m_apb_penable_next = 1'b1; + + s_apb_pready_next = 1'b0; + s_apb_prdata_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W] = m_apb.prdata; + if (m_apb.pslverr) begin + s_apb_pslverr_next = 1'b1; + end + s_apb_pruser_next = m_apb.pruser; + s_apb_pbuser_next = m_apb.pbuser; + + if (m_apb.psel && m_apb.penable && m_apb.pready) begin + m_apb_penable_next = 1'b0; + current_seg_next = current_seg_reg + 1; + m_apb_paddr_next = (m_apb_paddr_reg & M_ADDR_MASK) + SEG_STRB_W; + m_apb_pwdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W]; + m_apb_pstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W]; + if (current_seg_reg == SEG_COUNT_W'(SEG_COUNT-1)) begin + m_apb_psel_next = 1'b0; + s_apb_pready_next = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + data_reg <= data_next; + strb_reg <= strb_next; + + current_seg_reg <= current_seg_next; + + s_apb_pready_reg <= s_apb_pready_next; + s_apb_prdata_reg <= s_apb_prdata_next; + s_apb_pslverr_reg <= s_apb_pslverr_next; + s_apb_pruser_reg <= s_apb_pruser_next; + s_apb_pbuser_reg <= s_apb_pbuser_next; + + m_apb_paddr_reg <= m_apb_paddr_next; + m_apb_pprot_reg <= m_apb_pprot_next; + m_apb_psel_reg <= m_apb_psel_next; + m_apb_penable_reg <= m_apb_penable_next; + m_apb_pwrite_reg <= m_apb_pwrite_next; + m_apb_pwdata_reg <= m_apb_pwdata_next; + m_apb_pstrb_reg <= m_apb_pstrb_next; + m_apb_pauser_reg <= m_apb_pauser_next; + m_apb_pwuser_reg <= m_apb_pwuser_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_apb_pready_reg <= 1'b0; + + m_apb_psel_reg <= 1'b0; + m_apb_penable_reg <= 1'b0; + end + end + +end + +endmodule + +`resetall diff --git a/src/apb/tb/taxi_apb_adapter/Makefile b/src/apb/tb/taxi_apb_adapter/Makefile new file mode 100644 index 0000000..eebcd4a --- /dev/null +++ b/src/apb/tb/taxi_apb_adapter/Makefile @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_apb_adapter +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_ADDR_W := 32 +export PARAM_S_DATA_W := 32 +export PARAM_S_STRB_W := $(shell expr $(PARAM_S_DATA_W) / 8 ) +export PARAM_M_DATA_W := 32 +export PARAM_M_STRB_W := $(shell expr $(PARAM_M_DATA_W) / 8 ) +export PARAM_PAUSER_EN := 0 +export PARAM_PAUSER_W := 1 +export PARAM_PWUSER_EN := 0 +export PARAM_PWUSER_W := 1 +export PARAM_PBUSER_EN := 0 +export PARAM_PBUSER_W := 1 +export PARAM_PRUSER_EN := 0 +export PARAM_PRUSER_W := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.py b/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.py new file mode 100644 index 0000000..bdde469 --- /dev/null +++ b/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.py @@ -0,0 +1,237 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import ApbBus, ApbMaster, ApbRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst) + self.apb_ram = ApbRam(ApbBus.from_entity(dut.m_apb), dut.clk, dut.rst, size=2**16) + + def set_idle_generator(self, generator=None): + if generator: + self.apb_master.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.apb_ram.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.apb_master.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.apb_ram.write(addr-128, b'\xaa'*(length+256)) + + await tb.apb_master.write(addr, test_data) + + tb.log.debug("%s", tb.apb_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.apb_ram.read(addr, length) == test_data + assert tb.apb_ram.read(addr-1, 1) == b'\xaa' + assert tb.apb_ram.read(addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.apb_master.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.apb_ram.write(addr, test_data) + + data = await tb.apb_master.read(addr, length) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.apb_master, k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("m_data_w", [8, 16, 32]) +@pytest.mark.parametrize("s_data_w", [8, 16, 32]) +def test_taxi_apb_adapter(request, s_data_w, m_data_w): + dut = "taxi_apb_adapter" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_apb_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['ADDR_W'] = 32 + parameters['S_DATA_W'] = s_data_w + parameters['S_STRB_W'] = parameters['S_DATA_W'] // 8 + parameters['M_DATA_W'] = m_data_w + parameters['M_STRB_W'] = parameters['M_DATA_W'] // 8 + parameters["PAUSER_EN"] = 0 + parameters["PAUSER_W"] = 1 + parameters["PWUSER_EN"] = 0 + parameters["PWUSER_W"] = 1 + parameters["PRUSER_EN"] = 0 + parameters["PRUSER_W"] = 1 + parameters["PBUSER_EN"] = 0 + parameters["PBUSER_W"] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv b/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv new file mode 100644 index 0000000..c34d2f3 --- /dev/null +++ b/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * APB width adapter testbench + */ +module test_taxi_apb_adapter # +( + /* verilator lint_off WIDTHTRUNC */ + parameter ADDR_W = 32, + parameter S_DATA_W = 32, + parameter S_STRB_W = (S_DATA_W/8), + parameter M_DATA_W = 32, + parameter M_STRB_W = (M_DATA_W/8), + parameter logic PAUSER_EN = 1'b0, + parameter PAUSER_W = 1, + parameter logic PWUSER_EN = 1'b0, + parameter PWUSER_W = 1, + parameter logic PRUSER_EN = 1'b0, + parameter PRUSER_W = 1, + parameter logic PBUSER_EN = 1'b0, + parameter PBUSER_W = 1 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_apb_if #( + .DATA_W(S_DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(S_STRB_W), + .PAUSER_EN(PAUSER_EN), + .PAUSER_W(PAUSER_W), + .PWUSER_EN(PWUSER_EN), + .PWUSER_W(PWUSER_W), + .PRUSER_EN(PRUSER_EN), + .PRUSER_W(PRUSER_W), + .PBUSER_EN(PBUSER_EN), + .PBUSER_W(PBUSER_W) +) s_apb(); + +taxi_apb_if #( + .DATA_W(M_DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(M_STRB_W), + .PAUSER_EN(PAUSER_EN), + .PAUSER_W(PAUSER_W), + .PWUSER_EN(PWUSER_EN), + .PWUSER_W(PWUSER_W), + .PRUSER_EN(PRUSER_EN), + .PRUSER_W(PRUSER_W), + .PBUSER_EN(PBUSER_EN), + .PBUSER_W(PBUSER_W) +) m_apb(); + +taxi_apb_adapter +uut ( + .clk(clk), + .rst(rst), + + /* + * APB slave interface + */ + .s_apb(s_apb), + + /* + * APB master interface + */ + .m_apb(m_apb) +); + +endmodule + +`resetall