From b0bdf8ee1700249eb7fa5b730b23895c7846f22c Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 26 Mar 2025 00:13:12 -0700
Subject: [PATCH] Update readme

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index ed763cf..8939cd1 100644
--- a/README.md
+++ b/README.md
@@ -6,6 +6,8 @@ AXI, AXI stream, Ethernet, and PCIe components in System Verilog.
 
 GitHub repository: https://github.com/fpganinja/taxi
 
+Documentation: https://docs.taxi.fpga.ninja/
+
 ## Introduction
 
 The goal of the Taxi transport library is to provide a set of performant, easy-to-use building blocks in modern System Verilog facilitating data transport and interfacing, both internally via AXI and AXI stream, and externally via Ethernet, PCI express, UART, and I2C.  The building blocks are accompanied by testbenches and simulation models utilizing Cocotb and Verilator.