mirror of
https://github.com/fpganinja/taxi.git
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example/Alveo: Add example design for Xilinx Alveo series
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
280
example/Alveo/fpga/rtl/fpga_au200.sv
Normal file
280
example/Alveo/fpga/rtl/fpga_au200.sv
Normal file
@@ -0,0 +1,280 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Reset: Push button, active low
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*/
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic [3:0] sw,
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output wire logic [2:0] led,
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/*
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* I2C for board management
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*/
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inout wire logic i2c_scl,
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inout wire logic i2c_sda,
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/*
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* UART
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*/
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output wire logic uart_txd,
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input wire logic uart_rxd,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp0_tx_p,
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output wire logic [3:0] qsfp0_tx_n,
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input wire logic [3:0] qsfp0_rx_p,
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input wire logic [3:0] qsfp0_rx_n,
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input wire logic qsfp0_mgt_refclk_0_p,
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input wire logic qsfp0_mgt_refclk_0_n,
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// input wire logic qsfp0_mgt_refclk_1_p,
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// input wire logic qsfp0_mgt_refclk_1_n,
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output wire logic qsfp0_modsell,
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output wire logic qsfp0_resetl,
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input wire logic qsfp0_modprsl,
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input wire logic qsfp0_intl,
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output wire logic qsfp0_lpmode,
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// output wire logic qsfp0_refclk_reset,
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// output wire logic [1:0] qsfp0_fs,
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output wire logic [3:0] qsfp1_tx_p,
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output wire logic [3:0] qsfp1_tx_n,
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input wire logic [3:0] qsfp1_rx_p,
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input wire logic [3:0] qsfp1_rx_n,
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input wire logic qsfp1_mgt_refclk_0_p,
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input wire logic qsfp1_mgt_refclk_0_n,
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// input wire logic qsfp1_mgt_refclk_1_p,
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// input wire logic qsfp1_mgt_refclk_1_n,
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output wire logic qsfp1_modsell,
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output wire logic qsfp1_resetl,
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input wire logic qsfp1_modprsl,
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input wire logic qsfp1_intl,
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output wire logic qsfp1_lpmode
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// output wire logic qsfp1_refclk_reset,
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// output wire logic [1:0] qsfp1_fs
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);
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// Clock and reset
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wire clk_156mhz_ref_int;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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MMCME4_BASE #(
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// 156.25 MHz input
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.CLKIN1_PERIOD(6.4),
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.REF_JITTER1(0.010),
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// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(8),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 156.25 MHz input
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.CLKIN1(clk_156mhz_ref_int),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(4),
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.N(4),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({sw}),
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.out({sw_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o = 1'b1;
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wire i2c_scl_t = 1'b1;
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wire i2c_sda_i;
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wire i2c_sda_o = 1'b1;
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wire i2c_sda_t = 1'b1;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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wire qsfp0_mgt_refclk_0;
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wire qsfp1_mgt_refclk_0;
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assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.SW_CNT(4),
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.LED_CNT(3),
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.UART_CNT(1),
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.PORT_CNT(2),
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.GTY_QUAD_CNT(2),
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.GTY_CNT(2*4),
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.GTY_CLK_CNT(2)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk_125mhz(clk_125mhz_int),
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.rst_125mhz(rst_125mhz_int),
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/*
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* GPIO
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*/
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.sw(sw_int),
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.led(led),
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.port_led_act(),
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.port_led_stat_r(),
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.port_led_stat_g(),
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.port_led_stat_b(),
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.port_led_stat_y(),
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/*
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* UART
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*/
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.uart_txd(uart_txd),
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.uart_rxd(uart_rxd),
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/*
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* Ethernet
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*/
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.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
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.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
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.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
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.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
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.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
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.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
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.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
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.eth_port_modsell({qsfp1_modsell, qsfp0_modsell}),
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.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
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.eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
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.eth_port_intl({qsfp1_intl, qsfp0_intl}),
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.eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode})
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);
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endmodule
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`resetall
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243
example/Alveo/fpga/rtl/fpga_au280.sv
Normal file
243
example/Alveo/fpga/rtl/fpga_au280.sv
Normal file
@@ -0,0 +1,243 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
|
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)
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(
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/*
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* Reset: Push button, active low
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*/
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input wire logic reset,
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/*
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* GPIO
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*/
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output wire logic hbm_cattrip,
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/*
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* UART
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*/
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output wire logic uart_txd,
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input wire logic uart_rxd,
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/*
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* Ethernet: QSFP28
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||||
*/
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output wire logic [3:0] qsfp0_tx_p,
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output wire logic [3:0] qsfp0_tx_n,
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input wire logic [3:0] qsfp0_rx_p,
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input wire logic [3:0] qsfp0_rx_n,
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input wire logic qsfp0_mgt_refclk_0_p,
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input wire logic qsfp0_mgt_refclk_0_n,
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// input wire logic qsfp0_mgt_refclk_1_p,
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// input wire logic qsfp0_mgt_refclk_1_n,
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output wire logic qsfp0_refclk_oe_b,
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output wire logic qsfp0_refclk_fs,
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output wire logic [3:0] qsfp1_tx_p,
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output wire logic [3:0] qsfp1_tx_n,
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input wire logic [3:0] qsfp1_rx_p,
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input wire logic [3:0] qsfp1_rx_n,
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input wire logic qsfp1_mgt_refclk_0_p,
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input wire logic qsfp1_mgt_refclk_0_n,
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// input wire logic qsfp1_mgt_refclk_1_p,
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// input wire logic qsfp1_mgt_refclk_1_n,
|
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output wire logic qsfp1_refclk_oe_b,
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output wire logic qsfp1_refclk_fs
|
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);
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||||
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// Clock and reset
|
||||
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wire clk_156mhz_ref_int;
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// Internal 125 MHz clock
|
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = ~reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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|
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// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 156.25 MHz input
|
||||
.CLKIN1_PERIOD(6.4),
|
||||
.REF_JITTER1(0.010),
|
||||
// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(8),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
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.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 156.25 MHz input
|
||||
.CLKIN1(clk_156mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
assign qsfp0_refclk_oe_b = 1'b0;
|
||||
assign qsfp0_refclk_fs = 1'b1;
|
||||
assign qsfp1_refclk_oe_b = 1'b0;
|
||||
assign qsfp1_refclk_fs = 1'b1;
|
||||
|
||||
wire qsfp0_mgt_refclk_0;
|
||||
wire qsfp1_mgt_refclk_0;
|
||||
|
||||
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(1),
|
||||
.PORT_CNT(2),
|
||||
.GTY_QUAD_CNT(2),
|
||||
.GTY_CNT(2*4),
|
||||
.GTY_CLK_CNT(2)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
|
||||
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
|
||||
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
|
||||
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
|
||||
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
|
||||
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
229
example/Alveo/fpga/rtl/fpga_au45n.sv
Normal file
229
example/Alveo/fpga/rtl/fpga_au45n.sv
Normal file
@@ -0,0 +1,229 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter QSFP_CNT = 2,
|
||||
parameter UART_CNT = 1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic card_heart_bit,
|
||||
output wire logic card_status_led,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
// output wire logic [3:0] qsfp0_tx_p,
|
||||
// output wire logic [3:0] qsfp0_tx_n,
|
||||
// input wire logic [3:0] qsfp0_rx_p,
|
||||
// input wire logic [3:0] qsfp0_rx_n,
|
||||
// input wire logic qsfp0_mgt_refclk_0_p,
|
||||
// input wire logic qsfp0_mgt_refclk_0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_1_n,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_p,
|
||||
input wire logic qsfp1_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
wire qsfp1_mgt_refclk;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp1_mgt_refclk;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(2),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(QSFP_CNT),
|
||||
.GTY_QUAD_CNT(1),
|
||||
.GTY_CNT(1*4),
|
||||
.GTY_CLK_CNT(1)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led({card_heart_bit, card_status_led}),
|
||||
.port_led_act(qsfp_led_act),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(qsfp_led_stat_g),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p(qsfp1_tx_p),
|
||||
.eth_gty_tx_n(qsfp1_tx_n),
|
||||
.eth_gty_rx_p(qsfp1_rx_p),
|
||||
.eth_gty_rx_n(qsfp1_rx_n),
|
||||
.eth_gty_mgt_refclk_p(qsfp1_mgt_refclk_p),
|
||||
.eth_gty_mgt_refclk_n(qsfp1_mgt_refclk_n),
|
||||
.eth_gty_mgt_refclk_out(qsfp1_mgt_refclk),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
224
example/Alveo/fpga/rtl/fpga_au50.sv
Normal file
224
example/Alveo/fpga/rtl/fpga_au50.sv
Normal file
@@ -0,0 +1,224 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter QSFP_CNT = 1,
|
||||
parameter UART_CNT = 3
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
output wire logic hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_tx_p,
|
||||
output wire logic [3:0] qsfp_tx_n,
|
||||
input wire logic [3:0] qsfp_rx_p,
|
||||
input wire logic [3:0] qsfp_rx_n,
|
||||
input wire logic qsfp_mgt_refclk_0_p,
|
||||
input wire logic qsfp_mgt_refclk_0_n
|
||||
// input wire logic qsfp_mgt_refclk_1_p,
|
||||
// input wire logic qsfp_mgt_refclk_1_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
wire qsfp_mgt_refclk_0;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp_mgt_refclk_0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(QSFP_CNT),
|
||||
.GTY_QUAD_CNT(QSFP_CNT),
|
||||
.GTY_CNT(QSFP_CNT*4),
|
||||
.GTY_CLK_CNT(QSFP_CNT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(qsfp_led_act),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(qsfp_led_stat_g),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p(qsfp_tx_p),
|
||||
.eth_gty_tx_n(qsfp_tx_n),
|
||||
.eth_gty_rx_p(qsfp_rx_p),
|
||||
.eth_gty_rx_n(qsfp_rx_n),
|
||||
.eth_gty_mgt_refclk_p(qsfp_mgt_refclk_0_p),
|
||||
.eth_gty_mgt_refclk_n(qsfp_mgt_refclk_0_n),
|
||||
.eth_gty_mgt_refclk_out(qsfp_mgt_refclk_0),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
235
example/Alveo/fpga/rtl/fpga_au55.sv
Normal file
235
example/Alveo/fpga/rtl/fpga_au55.sv
Normal file
@@ -0,0 +1,235 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter QSFP_CNT = 2,
|
||||
parameter UART_CNT = 3
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
output wire logic hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_p,
|
||||
input wire logic qsfp0_mgt_refclk_n,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_p,
|
||||
input wire logic qsfp1_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
wire qsfp0_mgt_refclk;
|
||||
wire qsfp1_mgt_refclk;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp0_mgt_refclk;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(QSFP_CNT),
|
||||
.GTY_QUAD_CNT(QSFP_CNT),
|
||||
.GTY_CNT(QSFP_CNT*4),
|
||||
.GTY_CLK_CNT(QSFP_CNT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(qsfp_led_act),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(qsfp_led_stat_g),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
|
||||
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
|
||||
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
|
||||
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_p, qsfp0_mgt_refclk_p}),
|
||||
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_n, qsfp0_mgt_refclk_n}),
|
||||
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk, qsfp0_mgt_refclk}),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
419
example/Alveo/fpga/rtl/fpga_core.sv
Normal file
419
example/Alveo/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,419 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter SW_CNT = 4,
|
||||
parameter LED_CNT = 3,
|
||||
parameter UART_CNT = 1,
|
||||
parameter PORT_CNT = 2,
|
||||
parameter PORT_LED_CNT = PORT_CNT,
|
||||
parameter GTY_QUAD_CNT = PORT_CNT,
|
||||
parameter GTY_CNT = GTY_QUAD_CNT*4,
|
||||
parameter GTY_CLK_CNT = GTY_QUAD_CNT
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire clk_125mhz,
|
||||
input wire rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire [SW_CNT-1:0] sw,
|
||||
output wire [LED_CNT-1:0] led,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_act,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_r,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_g,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_b,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_y,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire [UART_CNT-1:0] uart_txd,
|
||||
input wire [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
|
||||
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
|
||||
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
|
||||
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
|
||||
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
|
||||
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
|
||||
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
|
||||
|
||||
output wire logic [PORT_CNT-1:0] eth_port_modsell,
|
||||
output wire logic [PORT_CNT-1:0] eth_port_resetl,
|
||||
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
|
||||
input wire logic [PORT_CNT-1:0] eth_port_intl,
|
||||
output wire logic [PORT_CNT-1:0] eth_port_lpmode
|
||||
);
|
||||
|
||||
// UART
|
||||
for (genvar n = 0; n < UART_CNT; n = n + 1) begin : uart_ch
|
||||
|
||||
taxi_axis_if #(.DATA_W(8)) axis_uart();
|
||||
|
||||
taxi_uart
|
||||
uut (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis_tx(axis_uart),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis_rx(axis_uart),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.rxd(uart_rxd[n]),
|
||||
.txd(uart_txd[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_busy(),
|
||||
.rx_busy(),
|
||||
.rx_overrun_error(),
|
||||
.rx_frame_error(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/115200/8))
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
// Ethernet
|
||||
assign eth_port_modsell = '1;
|
||||
assign eth_port_resetl = '1;
|
||||
assign eth_port_lpmode = '0;
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_clk;
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_rst;
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT-1:0]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT-1:0]();
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_clk;
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_rst;
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT-1:0]();
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_status;
|
||||
|
||||
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
|
||||
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
|
||||
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
|
||||
|
||||
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
|
||||
|
||||
wire eth_gty_mgt_refclk_int;
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
|
||||
assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
|
||||
assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
|
||||
.I (eth_gty_mgt_refclk_p[n]),
|
||||
.IB (eth_gty_mgt_refclk_n[n]),
|
||||
.CEB (1'b0),
|
||||
.O (eth_gty_mgt_refclk[n]),
|
||||
.ODIV2 (eth_gty_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
|
||||
.CE (ð_gty_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (eth_gty_mgt_refclk_int),
|
||||
.O (eth_gty_mgt_refclk_bufg[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
assign eth_gty_mgt_refclk_out[n] = eth_gty_mgt_refclk_bufg[n];
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(eth_gty_mgt_refclk_bufg[n]),
|
||||
.rst(rst_125mhz),
|
||||
.out(eth_gty_rst[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
|
||||
|
||||
localparam CLK = n;
|
||||
localparam CNT = 4;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(CNT),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4)
|
||||
)
|
||||
mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(eth_gty_rst[CLK]),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
|
||||
.xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
|
||||
.xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
|
||||
.xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
|
||||
.xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
|
||||
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
|
||||
.m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('0),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('0),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('0),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_bad_block(),
|
||||
.rx_sequence_error(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(eth_gty_rx_status[n*CNT +: CNT]),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg('{CNT{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : gty_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(eth_gty_rx_clk[n]),
|
||||
.s_rst(eth_gty_rx_rst[n]),
|
||||
.s_axis(eth_gty_axis_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(eth_gty_tx_clk[n]),
|
||||
.m_rst(eth_gty_tx_rst[n]),
|
||||
.m_axis(eth_gty_axis_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
222
example/Alveo/fpga/rtl/fpga_x3522.sv
Normal file
222
example/Alveo/fpga/rtl/fpga_x3522.sv
Normal file
@@ -0,0 +1,222 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter PORT_CNT = 4,
|
||||
parameter UART_CNT = 1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [PORT_CNT-1:0] dsfp_led_r,
|
||||
output wire logic [PORT_CNT-1:0] dsfp_led_g,
|
||||
output wire logic [PORT_CNT-1:0] dsfp_led_b,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [1:0] dsfp0_tx_p,
|
||||
output wire logic [1:0] dsfp0_tx_n,
|
||||
input wire logic [1:0] dsfp0_rx_p,
|
||||
input wire logic [1:0] dsfp0_rx_n,
|
||||
output wire logic [1:0] dsfp1_tx_p,
|
||||
output wire logic [1:0] dsfp1_tx_n,
|
||||
input wire logic [1:0] dsfp1_rx_p,
|
||||
input wire logic [1:0] dsfp1_rx_n,
|
||||
input wire logic dsfp_mgt_refclk_p,
|
||||
input wire logic dsfp_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
wire dsfp_mgt_refclk;
|
||||
|
||||
assign clk_161mhz_ref_int = dsfp_mgt_refclk;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(2),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(PORT_CNT),
|
||||
.GTY_QUAD_CNT(1),
|
||||
.GTY_CNT(1*4),
|
||||
.GTY_CLK_CNT(1)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(),
|
||||
.port_led_stat_r(dsfp_led_r),
|
||||
.port_led_stat_g(dsfp_led_g),
|
||||
.port_led_stat_b(dsfp_led_b),
|
||||
.port_led_stat_y(),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({dsfp1_tx_p, dsfp0_tx_p}),
|
||||
.eth_gty_tx_n({dsfp1_tx_n, dsfp0_tx_n}),
|
||||
.eth_gty_rx_p({dsfp1_rx_p, dsfp0_rx_p}),
|
||||
.eth_gty_rx_n({dsfp1_rx_n, dsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p(dsfp_mgt_refclk_p),
|
||||
.eth_gty_mgt_refclk_n(dsfp_mgt_refclk_n),
|
||||
.eth_gty_mgt_refclk_out(dsfp_mgt_refclk),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user