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https://github.com/fpganinja/taxi.git
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example/Alveo: Add example design for Xilinx Alveo series
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
419
example/Alveo/fpga/rtl/fpga_core.sv
Normal file
419
example/Alveo/fpga/rtl/fpga_core.sv
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@@ -0,0 +1,419 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus",
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parameter SW_CNT = 4,
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parameter LED_CNT = 3,
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parameter UART_CNT = 1,
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parameter PORT_CNT = 2,
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parameter PORT_LED_CNT = PORT_CNT,
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parameter GTY_QUAD_CNT = PORT_CNT,
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parameter GTY_CNT = GTY_QUAD_CNT*4,
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parameter GTY_CLK_CNT = GTY_QUAD_CNT
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)
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(
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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input wire clk_125mhz,
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input wire rst_125mhz,
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/*
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* GPIO
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*/
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input wire [SW_CNT-1:0] sw,
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output wire [LED_CNT-1:0] led,
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output wire [PORT_LED_CNT-1:0] port_led_act,
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output wire [PORT_LED_CNT-1:0] port_led_stat_r,
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output wire [PORT_LED_CNT-1:0] port_led_stat_g,
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output wire [PORT_LED_CNT-1:0] port_led_stat_b,
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output wire [PORT_LED_CNT-1:0] port_led_stat_y,
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/*
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* UART
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*/
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output wire [UART_CNT-1:0] uart_txd,
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input wire [UART_CNT-1:0] uart_rxd,
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/*
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* Ethernet
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*/
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output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
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output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
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input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
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input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
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input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
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input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
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output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
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output wire logic [PORT_CNT-1:0] eth_port_modsell,
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output wire logic [PORT_CNT-1:0] eth_port_resetl,
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input wire logic [PORT_CNT-1:0] eth_port_modprsl,
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input wire logic [PORT_CNT-1:0] eth_port_intl,
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output wire logic [PORT_CNT-1:0] eth_port_lpmode
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);
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// UART
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for (genvar n = 0; n < UART_CNT; n = n + 1) begin : uart_ch
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taxi_axis_if #(.DATA_W(8)) axis_uart();
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taxi_uart
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uut (
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.clk(clk_125mhz),
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.rst(rst_125mhz),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis_tx(axis_uart),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis_rx(axis_uart),
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/*
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* UART interface
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*/
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.rxd(uart_rxd[n]),
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.txd(uart_txd[n]),
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/*
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* Status
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*/
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.tx_busy(),
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.rx_busy(),
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.rx_overrun_error(),
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.rx_frame_error(),
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/*
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* Configuration
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*/
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.prescale(16'(125000000/115200/8))
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);
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end
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// Ethernet
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assign eth_port_modsell = '1;
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assign eth_port_resetl = '1;
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assign eth_port_lpmode = '0;
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wire [GTY_CNT-1:0] eth_gty_tx_clk;
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wire [GTY_CNT-1:0] eth_gty_tx_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT-1:0]();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT-1:0]();
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wire [GTY_CNT-1:0] eth_gty_rx_clk;
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wire [GTY_CNT-1:0] eth_gty_rx_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT-1:0]();
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wire [GTY_CNT-1:0] eth_gty_rx_status;
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wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
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wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
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wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
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wire [GTY_CLK_CNT-1:0] eth_gty_rst;
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for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
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wire eth_gty_mgt_refclk_int;
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if (SIM) begin
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assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
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assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
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assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
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end else begin
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IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
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.I (eth_gty_mgt_refclk_p[n]),
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.IB (eth_gty_mgt_refclk_n[n]),
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.CEB (1'b0),
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.O (eth_gty_mgt_refclk[n]),
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.ODIV2 (eth_gty_mgt_refclk_int)
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);
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BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
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.CE (ð_gty_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (eth_gty_mgt_refclk_int),
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.O (eth_gty_mgt_refclk_bufg[n])
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);
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end
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assign eth_gty_mgt_refclk_out[n] = eth_gty_mgt_refclk_bufg[n];
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taxi_sync_reset #(
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.N(4)
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)
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qsfp_sync_reset_inst (
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.clk(eth_gty_mgt_refclk_bufg[n]),
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.rst(rst_125mhz),
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.out(eth_gty_rst[n])
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);
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end
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for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
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localparam CLK = n;
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localparam CNT = 4;
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taxi_eth_mac_25g_us #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.CNT(CNT),
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// GT type
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.GT_TYPE("GTY"),
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// PHY parameters
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.PADDING_EN(1'b1),
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.DIC_EN(1'b1),
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.MIN_FRAME_LEN(64),
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.PTP_TS_EN(1'b0),
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.PTP_TS_FMT_TOD(1'b1),
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.PTP_TS_W(96),
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.PRBS31_EN(1'b0),
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.TX_SERDES_PIPELINE(1),
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.RX_SERDES_PIPELINE(1),
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.COUNT_125US(125000/6.4)
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)
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mac_inst (
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.xcvr_ctrl_clk(clk_125mhz),
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.xcvr_ctrl_rst(eth_gty_rst[CLK]),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
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.xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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/*
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* Serial data
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*/
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.xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
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.xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
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.xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
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.xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
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/*
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* MAC clocks
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*/
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.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
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.rx_rst_in('0),
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.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
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.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
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.tx_rst_in('0),
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.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
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.ptp_sample_clk('0),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
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.m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
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/*
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* PTP clock
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*/
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.tx_ptp_ts('0),
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.tx_ptp_ts_step('0),
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.rx_ptp_ts('0),
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.rx_ptp_ts_step('0),
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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.tx_lfc_req('0),
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.tx_lfc_resend('0),
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.rx_lfc_en('0),
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.rx_lfc_req(),
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.rx_lfc_ack('0),
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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.tx_pfc_req('0),
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.tx_pfc_resend('0),
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.rx_pfc_en('0),
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.rx_pfc_req(),
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.rx_pfc_ack('0),
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/*
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* Pause interface
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*/
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.tx_lfc_pause_en('0),
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.tx_pause_req('0),
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.tx_pause_ack(),
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/*
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* Status
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*/
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.tx_start_packet(),
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.tx_error_underflow(),
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.rx_start_packet(),
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.rx_error_count(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_bad_block(),
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.rx_sequence_error(),
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.rx_block_lock(),
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.rx_high_ber(),
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.rx_status(eth_gty_rx_status[n*CNT +: CNT]),
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.stat_tx_mcf(),
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.stat_rx_mcf(),
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.stat_tx_lfc_pkt(),
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.stat_tx_lfc_xon(),
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.stat_tx_lfc_xoff(),
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.stat_tx_lfc_paused(),
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.stat_tx_pfc_pkt(),
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.stat_tx_pfc_xon(),
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.stat_tx_pfc_xoff(),
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.stat_tx_pfc_paused(),
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.stat_rx_lfc_pkt(),
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.stat_rx_lfc_xon(),
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.stat_rx_lfc_xoff(),
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.stat_rx_lfc_paused(),
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.stat_rx_pfc_pkt(),
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.stat_rx_pfc_xon(),
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.stat_rx_pfc_xoff(),
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.stat_rx_pfc_paused(),
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/*
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* Configuration
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*/
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.cfg_ifg('{CNT{8'd12}}),
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.cfg_tx_enable('1),
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.cfg_rx_enable('1),
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.cfg_tx_prbs31_enable('0),
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.cfg_rx_prbs31_enable('0),
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.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
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.cfg_mcf_rx_check_eth_dst_mcast('1),
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.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
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.cfg_mcf_rx_check_eth_dst_ucast('0),
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.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
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.cfg_mcf_rx_check_eth_src('0),
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.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
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.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
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.cfg_mcf_rx_check_opcode_lfc('1),
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.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
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.cfg_mcf_rx_check_opcode_pfc('1),
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.cfg_mcf_rx_forward('0),
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.cfg_mcf_rx_enable('0),
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.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
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.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
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.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
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.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
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.cfg_tx_lfc_en('0),
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.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
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.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
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.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
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.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
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.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
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.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
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.cfg_tx_pfc_en('0),
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.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
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.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
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.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
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.cfg_rx_lfc_en('0),
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.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
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.cfg_rx_pfc_en('0)
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);
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end
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for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : gty_ch
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taxi_axis_async_fifo #(
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.DEPTH(16384),
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.RAM_PIPELINE(2),
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.FRAME_FIFO(1),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_OVERSIZE_FRAME(1),
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.DROP_BAD_FRAME(1),
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.DROP_WHEN_FULL(1)
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)
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ch_fifo (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(eth_gty_rx_clk[n]),
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.s_rst(eth_gty_rx_rst[n]),
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.s_axis(eth_gty_axis_rx[n]),
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/*
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* AXI4-Stream output (source)
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*/
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.m_clk(eth_gty_tx_clk[n]),
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.m_rst(eth_gty_tx_rst[n]),
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.m_axis(eth_gty_axis_tx[n]),
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/*
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* Pause
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*/
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.s_pause_req(1'b0),
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.s_pause_ack(),
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.m_pause_req(1'b0),
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.m_pause_ack(),
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/*
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* Status
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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.m_status_depth_commit(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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end
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endmodule
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`resetall
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