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pcie: Rename enable to en in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -36,7 +36,7 @@ module taxi_pcie_us_axil_master
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* Configuration
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* Configuration
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*/
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*/
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input wire logic [15:0] completer_id,
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input wire logic [15:0] completer_id,
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input wire logic completer_id_enable,
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input wire logic completer_id_en,
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/*
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/*
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* Status
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* Status
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@@ -262,7 +262,7 @@ always_comb begin
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cpl_tlp_hdr[63:48] = requester_id_reg;
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cpl_tlp_hdr[63:48] = requester_id_reg;
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cpl_tlp_hdr[71:64] = tag_reg;
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cpl_tlp_hdr[71:64] = tag_reg;
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cpl_tlp_hdr[87:72] = completer_id;
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cpl_tlp_hdr[87:72] = completer_id;
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cpl_tlp_hdr[88] = completer_id_enable;
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cpl_tlp_hdr[88] = completer_id_en;
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cpl_tlp_hdr[91:89] = tc_reg;
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cpl_tlp_hdr[91:89] = tc_reg;
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cpl_tlp_hdr[94:92] = attr_reg;
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cpl_tlp_hdr[94:92] = attr_reg;
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cpl_tlp_hdr[95] = 1'b0; // force ECRC
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cpl_tlp_hdr[95] = 1'b0; // force ECRC
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@@ -124,7 +124,7 @@ class TB(object):
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self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
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self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
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dut.completer_id.setimmediatevalue(0)
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dut.completer_id.setimmediatevalue(0)
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dut.completer_id_enable.setimmediatevalue(0)
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dut.completer_id_en.setimmediatevalue(0)
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# monitor error outputs
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# monitor error outputs
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self.stat_err_cor_asserted = False
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self.stat_err_cor_asserted = False
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@@ -59,7 +59,7 @@ taxi_axil_if #(
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) m_axil();
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) m_axil();
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logic [15:0] completer_id;
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logic [15:0] completer_id;
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logic completer_id_enable;
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logic completer_id_en;
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logic stat_err_cor;
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logic stat_err_cor;
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logic stat_err_uncor;
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logic stat_err_uncor;
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@@ -85,7 +85,7 @@ uut (
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* Configuration
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* Configuration
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*/
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*/
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.completer_id(completer_id),
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.completer_id(completer_id),
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.completer_id_enable(completer_id_enable),
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.completer_id_en(completer_id_en),
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/*
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/*
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* Status
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* Status
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