diff --git a/example/ZCU111/fpga/README.md b/example/ZCU111/fpga/README.md index 4b184f9..4e0475f 100644 --- a/example/ZCU111/fpga/README.md +++ b/example/ZCU111/fpga/README.md @@ -4,10 +4,10 @@ This example design targets the Xilinx ZCU111 FPGA board. -The design places looped-back MACs on the SFP+ ports as well as a looped-back UART on on the USB UART connection. +The design places looped-back MACs on the SFP+ ports, as well as XFCP on the USB UART for monitoring and control. * USB UART - * Looped-back UART + * XFCP (3 Mbaud) * QSFP28 * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers @@ -40,6 +40,4 @@ DIP switch settings: Run `make program` to program the board with Vivado. -To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification. - To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/example/ZCU111/fpga/fpga/Makefile b/example/ZCU111/fpga/fpga/Makefile index 144d70e..da82f1a 100644 --- a/example/ZCU111/fpga/fpga/Makefile +++ b/example/ZCU111/fpga/fpga/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = zynquplus SYN_FILES = ../rtl/fpga.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/ZCU111/fpga/fpga_10g/Makefile b/example/ZCU111/fpga/fpga_10g/Makefile index 845bb86..4966e0e 100644 --- a/example/ZCU111/fpga/fpga_10g/Makefile +++ b/example/ZCU111/fpga/fpga_10g/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = zynquplus SYN_FILES = ../rtl/fpga.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/ZCU111/fpga/rtl/fpga_core.sv b/example/ZCU111/fpga/rtl/fpga_core.sv index 4abde66..5857413 100644 --- a/example/ZCU111/fpga/rtl/fpga_core.sv +++ b/example/ZCU111/fpga/rtl/fpga_core.sv @@ -66,44 +66,108 @@ module fpga_core # assign led = sw; -// UART -assign uart_cts = 0; +// XFCP +assign uart_cts = 1'b0; -taxi_axis_if #(.DATA_W(8)) axis_uart(); +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us(); -taxi_uart -uart_inst ( +taxi_xfcp_if_uart #( + .TX_FIFO_DEPTH(512), + .RX_FIFO_DEPTH(512) +) +xfcp_if_uart_inst ( .clk(clk_125mhz), .rst(rst_125mhz), - /* - * AXI4-Stream input (sink) - */ - .s_axis_tx(axis_uart), - - /* - * AXI4-Stream output (source) - */ - .m_axis_rx(axis_uart), - /* * UART interface */ - .rxd(uart_rxd), - .txd(uart_txd), + .uart_rxd(uart_rxd), + .uart_txd(uart_txd), /* - * Status + * XFCP downstream interface */ - .tx_busy(), - .rx_busy(), - .rx_overrun_error(), - .rx_frame_error(), + .xfcp_dsp_ds(xfcp_ds), + .xfcp_dsp_us(xfcp_us), /* * Configuration */ - .prescale(16'(125000000/115200)) + .prescale(16'(125000000/3000000)) +); + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1](); + +taxi_xfcp_switch #( + .XFCP_ID_STR("ZCU111"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR("Taxi example"), + .PORTS($size(xfcp_sw_us)) +) +xfcp_sw_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_ds), + .xfcp_usp_us(xfcp_us), + + /* + * XFCP downstream ports + */ + .xfcp_dsp_ds(xfcp_sw_ds), + .xfcp_dsp_us(xfcp_sw_us) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat(); + +taxi_xfcp_mod_stats #( + .XFCP_ID_STR("Statistics"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR(""), + .STAT_COUNT_W(64), + .STAT_PIPELINE(2) +) +xfcp_stats_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[0]), + .xfcp_usp_us(xfcp_sw_us[0]), + + /* + * Statistics increment input + */ + .s_axis_stat(axis_stat) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[1](); + +taxi_axis_arb_mux #( + .S_COUNT($size(axis_eth_stat)), + .UPDATE_TID(1'b0), + .ARB_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIO(1'b0) +) +stat_mux_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * AXI4-Stream inputs (sink) + */ + .s_axis(axis_eth_stat), + + /* + * AXI4-Stream output (source) + */ + .m_axis(axis_stat) ); // SFP+ @@ -127,7 +191,6 @@ wire sfp_rst; taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[4](); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[4](); taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[4](); -taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat(); if (SIM) begin @@ -187,7 +250,11 @@ taxi_eth_mac_25g_us #( .TX_SERDES_PIPELINE(1), .RX_SERDES_PIPELINE(1), .COUNT_125US(125000/6.4), - .STAT_EN(1'b0) + .STAT_EN(1), + .STAT_TX_LEVEL(1), + .STAT_RX_LEVEL(1), + .STAT_ID_BASE(0), + .STAT_UPDATE_PERIOD(1024) ) sfp_mac_inst ( .xcvr_ctrl_clk(clk_125mhz), @@ -270,7 +337,7 @@ sfp_mac_inst ( */ .stat_clk(clk_125mhz), .stat_rst(rst_125mhz), - .m_axis_stat(axis_sfp_stat), + .m_axis_stat(axis_eth_stat[0]), /* * Status diff --git a/example/ZCU111/fpga/tb/fpga_core/Makefile b/example/ZCU111/fpga/tb/fpga_core/Makefile index 7f869f7..8d49e56 100644 --- a/example/ZCU111/fpga/tb/fpga_core/Makefile +++ b/example/ZCU111/fpga/tb/fpga_core/Makefile @@ -20,7 +20,9 @@ MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += ../../rtl/$(DUT).sv VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f -VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv diff --git a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py index 25e0e12..7a7d9ff 100644 --- a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py @@ -55,8 +55,8 @@ class TB: self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) - self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1) - self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1) + self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1) + self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -84,25 +84,6 @@ class TB: await RisingEdge(self.dut.clk_125mhz) -async def uart_test(tb, source, sink): - tb.log.info("Test UART") - - tx_data = b"FPGA Ninja" - - tb.log.info("UART TX: %s", tx_data) - - await source.write(tx_data) - - rx_data = bytearray() - - while len(rx_data) < len(tx_data): - rx_data.extend(await sink.read()) - - tb.log.info("UART RX: %s", rx_data) - - tb.log.info("UART test done") - - async def mac_test(tb, source, sink): tb.log.info("Test MAC") @@ -152,10 +133,6 @@ async def run_test(dut): tests = [] - tb.log.info("Start UART test") - - tests.append(cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink))) - for k in range(len(tb.sfp_sources)): tb.log.info("Start SFP %d 10G MAC loopback test", k) tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) @@ -194,7 +171,9 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"), - os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"), os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),