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eth: Clean up array init

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-08 14:42:08 -07:00
parent 4b7ca2a569
commit bb278958b2
4 changed files with 11 additions and 38 deletions
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15
src/eth/rtl/taxi_eth_phy_10g_rx_if.sv
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@@ -95,22 +95,15 @@ end
if (SERDES_PIPELINE > 0) begin if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *) (* srl_style = "register" *)
logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0]; logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0]; logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic serdes_rx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_rx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] = '0;
serdes_rx_data_valid_pipe_reg[n] = '0;
serdes_rx_hdr_pipe_reg[n] = '0;
serdes_rx_hdr_valid_pipe_reg[n] = '0;
end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1]; serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_data_valid_pipe_reg[n] <= n == 0 ? serdes_rx_data_valid : serdes_rx_data_valid_pipe_reg[n-1]; serdes_rx_data_valid_pipe_reg[n] <= n == 0 ? serdes_rx_data_valid : serdes_rx_data_valid_pipe_reg[n-1];

18
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
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@@ -100,25 +100,17 @@ end
if (SERDES_PIPELINE > 0) begin if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *) (* srl_style = "register" *)
logic [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0]; logic [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0]; logic [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
(* srl_style = "register" *) (* srl_style = "register" *)
logic serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0]; logic serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_tx_data_pipe_reg[n] = '0;
serdes_tx_data_valid_pipe_reg[n] = '0;
serdes_tx_hdr_pipe_reg[n] = '0;
serdes_tx_hdr_valid_pipe_reg[n] = '0;
serdes_tx_gbx_sync_pipe_reg[n] = '0;
end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1]; serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1]; serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1];

8
src/eth/rtl/taxi_mac_pause_ctrl_rx.sv
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@@ -85,7 +85,7 @@ logic [QFB-1:0] quanta_cnt_reg = '0, quanta_cnt_next;
logic [1:0] quanta_inc_reg = '0, quanta_inc_next; logic [1:0] quanta_inc_reg = '0, quanta_inc_next;
logic [QW-1:0] lfc_quanta_reg = '0, lfc_quanta_next; logic [QW-1:0] lfc_quanta_reg = '0, lfc_quanta_next;
logic [QW-1:0] pfc_quanta_reg[8], pfc_quanta_next[8]; logic [QW-1:0] pfc_quanta_reg[8] = '{default: '0}, pfc_quanta_next[8];
logic stat_rx_lfc_pkt_reg = 1'b0, stat_rx_lfc_pkt_next; logic stat_rx_lfc_pkt_reg = 1'b0, stat_rx_lfc_pkt_next;
logic stat_rx_lfc_xon_reg = 1'b0, stat_rx_lfc_xon_next; logic stat_rx_lfc_xon_reg = 1'b0, stat_rx_lfc_xon_next;
@@ -106,12 +106,6 @@ assign stat_rx_pfc_xon = stat_rx_pfc_xon_reg;
assign stat_rx_pfc_xoff = stat_rx_pfc_xoff_reg; assign stat_rx_pfc_xoff = stat_rx_pfc_xoff_reg;
assign stat_rx_pfc_paused = pfc_req_reg; assign stat_rx_pfc_paused = pfc_req_reg;
initial begin
for (integer k = 0; k < 8; k = k + 1) begin
pfc_quanta_reg[k] = '0;
end
end
always_comb begin always_comb begin
stat_rx_lfc_pkt_next = 1'b0; stat_rx_lfc_pkt_next = 1'b0;
stat_rx_lfc_xon_next = 1'b0; stat_rx_lfc_xon_next = 1'b0;

8
src/eth/rtl/taxi_mac_pause_ctrl_tx.sv
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@@ -99,7 +99,7 @@ logic [QFB-1:0] quanta_cnt_reg = '0, quanta_cnt_next;
logic [1:0] quanta_inc_reg = '0, quanta_inc_next; logic [1:0] quanta_inc_reg = '0, quanta_inc_next;
logic [QW-1:0] lfc_refresh_reg = '0, lfc_refresh_next; logic [QW-1:0] lfc_refresh_reg = '0, lfc_refresh_next;
logic [QW-1:0] pfc_refresh_reg[8], pfc_refresh_next[8]; logic [QW-1:0] pfc_refresh_reg[8] = '{default: '0}, pfc_refresh_next[8];
logic stat_tx_lfc_pkt_reg = 1'b0, stat_tx_lfc_pkt_next; logic stat_tx_lfc_pkt_reg = 1'b0, stat_tx_lfc_pkt_next;
logic stat_tx_lfc_xon_reg = 1'b0, stat_tx_lfc_xon_next; logic stat_tx_lfc_xon_reg = 1'b0, stat_tx_lfc_xon_next;
@@ -146,12 +146,6 @@ assign stat_tx_pfc_xon = stat_tx_pfc_xon_reg;
assign stat_tx_pfc_xoff = stat_tx_pfc_xoff_reg; assign stat_tx_pfc_xoff = stat_tx_pfc_xoff_reg;
assign stat_tx_pfc_paused = pfc_req_reg; assign stat_tx_pfc_paused = pfc_req_reg;
initial begin
for (integer k = 0; k < 8; k = k + 1) begin
pfc_refresh_reg[k] = 0;
end
end
always_comb begin always_comb begin
lfc_req_next = lfc_req_reg; lfc_req_next = lfc_req_reg;
lfc_act_next = lfc_act_reg; lfc_act_next = lfc_act_reg;