diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv index b5e4412..519411e 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au200.sv @@ -252,6 +252,12 @@ assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n; assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0]; +wire uart_txd_int[1]; +wire uart_rxd_int[1]; + +assign uart_txd = uart_txd_int[0]; +assign uart_rxd_int[0] = uart_rxd; + fpga_core #( .SIM(SIM), .VENDOR(VENDOR), @@ -289,8 +295,8 @@ core_inst ( /* * UART */ - .uart_txd(uart_txd), - .uart_rxd(uart_rxd), + .uart_txd(uart_txd_int), + .uart_rxd(uart_rxd_int), /* * Ethernet diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv index bebd73f..4e2a0c5 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au280.sv @@ -215,6 +215,12 @@ assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n; assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0]; +wire uart_txd_int[1]; +wire uart_rxd_int[1]; + +assign uart_txd = uart_txd_int[0]; +assign uart_rxd_int[0] = uart_rxd; + fpga_core #( .SIM(SIM), .VENDOR(VENDOR), @@ -252,8 +258,8 @@ core_inst ( /* * UART */ - .uart_txd(uart_txd), - .uart_rxd(uart_rxd), + .uart_txd(uart_txd_int), + .uart_rxd(uart_rxd_int), /* * Ethernet diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv index bd2cf2e..0d3e3f6 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv @@ -44,8 +44,8 @@ module fpga # /* * UART */ - output wire logic [UART_CNT-1:0] uart_txd, - input wire logic [UART_CNT-1:0] uart_rxd, + output wire logic uart_txd[UART_CNT], + input wire logic uart_rxd[UART_CNT], /* * Ethernet: QSFP28 diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv index 407d31e..a6ccd7c 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au50.sv @@ -43,8 +43,8 @@ module fpga # /* * UART */ - output wire logic [UART_CNT-1:0] uart_txd, - input wire logic [UART_CNT-1:0] uart_rxd, + output wire logic uart_txd[UART_CNT], + input wire logic uart_rxd[UART_CNT], /* * Ethernet: QSFP28 diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv b/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv index 255f586..f10968f 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv @@ -48,8 +48,8 @@ module fpga # /* * UART */ - output wire logic [UART_CNT-1:0] uart_txd, - input wire logic [UART_CNT-1:0] uart_rxd, + output wire logic uart_txd[UART_CNT], + input wire logic uart_rxd[UART_CNT], /* * Ethernet: QSFP28 diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index 0db81cb..b9b38ce 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -59,8 +59,8 @@ module fpga_core # /* * UART */ - output wire [UART_CNT-1:0] uart_txd, - input wire [UART_CNT-1:0] uart_rxd, + output wire uart_txd[UART_CNT], + input wire uart_rxd[UART_CNT], /* * Ethernet diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv b/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv index 581e647..3baed28 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv @@ -42,8 +42,8 @@ module fpga # /* * UART */ - output wire logic [UART_CNT-1:0] uart_txd, - input wire logic [UART_CNT-1:0] uart_rxd, + output wire logic uart_txd[UART_CNT], + input wire logic uart_rxd[UART_CNT], /* * Ethernet: QSFP28 diff --git a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index d3efdf0..9874281 100644 --- a/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -43,8 +43,8 @@ class TB: cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) - self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1) - self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1) + self.uart_sources = [UartSource(pin, baud=3000000, bits=8, stop_bits=1) for pin in dut.uart_rxd] + self.uart_sinks = [UartSink(pin, baud=3000000, bits=8, stop_bits=1) for pin in dut.uart_txd] self.qsfp_sources = [] self.qsfp_sinks = []