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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-07-30 19:12:45 -07:00
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@@ -6,7 +6,7 @@ AXI, AXI stream, Ethernet, and PCIe components in System Verilog.
GitHub repository: https://github.com/fpganinja/taxi
Documentation: https://docs.taxi.fpga.ninja/
Documentation: https://docs.fpga.taxi/
## Introduction