From be80d4e9649fb6b8dfa119b5b99fc55e93323db3 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 21 Feb 2026 02:48:18 -0800 Subject: [PATCH] pcie: Tie off AXIL user signals in PCIe AXI lite master module Signed-off-by: Alex Forencich --- src/pcie/rtl/taxi_pcie_us_axil_master.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/pcie/rtl/taxi_pcie_us_axil_master.sv b/src/pcie/rtl/taxi_pcie_us_axil_master.sv index 56183a4..a20bbee 100644 --- a/src/pcie/rtl/taxi_pcie_us_axil_master.sv +++ b/src/pcie/rtl/taxi_pcie_us_axil_master.sv @@ -201,13 +201,16 @@ assign s_axis_cq.tready = s_axis_cq_tready_reg; assign m_axil_wr.awaddr = m_axil_addr_reg; assign m_axil_wr.awprot = 3'b010; +assign m_axil_wr.awuser = '0; assign m_axil_wr.awvalid = m_axil_awvalid_reg; assign m_axil_wr.wdata = m_axil_wdata_reg; assign m_axil_wr.wstrb = m_axil_wstrb_reg; +assign m_axil_wr.wuser = '0; assign m_axil_wr.wvalid = m_axil_wvalid_reg; assign m_axil_wr.bready = m_axil_bready_reg; assign m_axil_rd.araddr = m_axil_addr_reg; assign m_axil_rd.arprot = 3'b010; +assign m_axil_rd.aruser = '0; assign m_axil_rd.arvalid = m_axil_arvalid_reg; assign m_axil_rd.rready = m_axil_rready_reg;