axis: Add AXI stream adapter module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/axis/taxi_axis_adapter/Makefile

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_axis_adapter
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_S_DATA_W := 8
+export PARAM_S_KEEP_EN := $(shell expr $(PARAM_S_DATA_W) \> 8 )
+export PARAM_S_KEEP_W := $(shell expr \( $(PARAM_S_DATA_W) + 7 \) / 8 )
+export PARAM_S_STRB_EN := 0
+export PARAM_M_DATA_W := 8
+export PARAM_M_KEEP_EN := $(shell expr $(PARAM_M_DATA_W) \> 8 )
+export PARAM_M_KEEP_W := $(shell expr \( $(PARAM_M_DATA_W) + 7 \) / 8 )
+export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
+export PARAM_ID_EN := 1
+export PARAM_ID_W := 8
+export PARAM_DEST_EN := 1
+export PARAM_DEST_W := 8
+export PARAM_USER_EN := 1
+export PARAM_USER_W := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.py

@@ -0,0 +1,264 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.source.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.sink.set_pause_generator(generator())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    id_count = 2**len(tb.source.bus.tid)
+
+    cur_id = 1
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_frames = []
+
+    for test_data in [payload_data(x) for x in payload_lengths()]:
+        test_frame = AxiStreamFrame(test_data)
+        test_frame.tid = cur_id
+        test_frame.tdest = cur_id
+
+        # set tkeep to all zeros when disabled to verify correct handling
+        if not int(dut.S_KEEP_EN.value):
+            test_frame.tkeep = [0]*len(test_data)
+
+        test_frames.append(test_frame)
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % id_count
+
+    for test_frame in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == test_frame.tdata
+        assert rx_frame.tid == test_frame.tid
+        assert rx_frame.tdest == test_frame.tdest
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_tuser_assert(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
+    test_frame = AxiStreamFrame(test_data, tuser=1)
+    await tb.source.send(test_frame)
+
+    rx_frame = await tb.sink.recv()
+
+    assert rx_frame.tdata == test_data
+    assert rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
+    id_count = 2**len(tb.source.bus.tid)
+
+    cur_id = 1
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_frames = []
+
+    for k in range(128):
+        length = random.randint(1, byte_lanes*16)
+        test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+        test_frame = AxiStreamFrame(test_data)
+        test_frame.tid = cur_id
+        test_frame.tdest = cur_id
+
+        test_frames.append(test_frame)
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % id_count
+
+    for test_frame in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == test_frame.tdata
+        assert rx_frame.tid == test_frame.tid
+        assert rx_frame.tdest == test_frame.tdest
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+def size_list():
+    data_width = max(len(cocotb.top.s_axis.tdata), len(cocotb.top.m_axis.tdata))
+    byte_width = data_width // 8
+    return list(range(1, byte_width*4+1))+[512]+[1]*64
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+    for test in [run_test_tuser_assert]:
+        factory = TestFactory(test)
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("m_data_width", [8, 16, 32])
+@pytest.mark.parametrize("s_data_width", [8, 16, 32])
+def test_taxi_axis_register(request, s_data_width, m_data_width):
+    dut = "taxi_axis_adapter"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "axis", f"{dut}.sv"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['S_DATA_W'] = s_data_width
+    parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
+    parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
+    parameters['S_STRB_EN'] = 0
+    parameters['M_DATA_W'] = m_data_width
+    parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
+    parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
+    parameters['M_STRB_EN'] = parameters['S_STRB_EN']
+    parameters['ID_EN'] = 1
+    parameters['ID_W'] = 8
+    parameters['DEST_EN'] = 1
+    parameters['DEST_W'] = 8
+    parameters['USER_EN'] = 1
+    parameters['USER_W'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/axis/taxi_axis_adapter/test_taxi_axis_adapter.sv

@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream FIFO testbench
+ */
+module test_taxi_axis_adapter #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter S_DATA_W = 8,
+    parameter logic S_KEEP_EN = (S_DATA_W>8),
+    parameter S_KEEP_W = ((S_DATA_W+7)/8),
+    parameter logic S_STRB_EN = 0,
+    parameter M_DATA_W = 8,
+    parameter logic M_KEEP_EN = (M_DATA_W>8),
+    parameter M_KEEP_W = ((M_DATA_W+7)/8),
+    parameter logic M_STRB_EN = 0,
+    parameter logic ID_EN = 0,
+    parameter ID_W = 8,
+    parameter logic DEST_EN = 0,
+    parameter DEST_W = 8,
+    parameter logic USER_EN = 1,
+    parameter USER_W = 1
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(
+    .DATA_W(S_DATA_W),
+    .KEEP_EN(S_KEEP_EN),
+    .KEEP_W(S_KEEP_W),
+    .STRB_EN(S_STRB_EN),
+    .LAST_EN(1'b1),
+    .ID_EN(ID_EN),
+    .ID_W(ID_W),
+    .DEST_EN(DEST_EN),
+    .DEST_W(DEST_W),
+    .USER_EN(USER_EN),
+    .USER_W(USER_W)
+) s_axis();
+
+taxi_axis_if #(
+    .DATA_W(M_DATA_W),
+    .KEEP_EN(M_KEEP_EN),
+    .KEEP_W(M_KEEP_W),
+    .STRB_EN(M_STRB_EN),
+    .LAST_EN(1'b1),
+    .ID_EN(ID_EN),
+    .ID_W(ID_W),
+    .DEST_EN(DEST_EN),
+    .DEST_W(DEST_W),
+    .USER_EN(USER_EN),
+    .USER_W(USER_W)
+) m_axis();
+
+taxi_axis_adapter
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis(s_axis),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(m_axis)
+);
+
+endmodule
+
+`resetall