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eth: Update KCU105 pins

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-13 19:44:48 -07:00
parent 8bc90d0627
commit c280dd3da3
3 changed files with 12 additions and 3 deletions
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6
src/eth/example/KCU105/fpga/fpga.xdc
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@@ -45,6 +45,10 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
#set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_user_sma_n] ;# J35 #set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_user_sma_n] ;# J35
#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p] #create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p]
# User SMA GPIO J36/J37
#set_property -dict {LOC H27 IOSTANDARD LVDS} [get_ports user_sma_gpio_p] ;# J36
#set_property -dict {LOC G27 IOSTANDARD LVDS} [get_ports user_sma_gpio_n] ;# J37
# LEDs # LEDs
set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to DS7 set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to DS7
set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to DS6 set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to DS6
@@ -172,7 +176,9 @@ set_property -dict {LOC P5 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_227
#set_property -dict {LOC AH11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U57 CKIN1 SI5328 #set_property -dict {LOC AH11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U57 CKIN1 SI5328
set_property -dict {LOC AL8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[0]}] set_property -dict {LOC AL8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[0]}]
set_property -dict {LOC K21 IOSTANDARD LVCMOS18} [get_ports {sfp_rx_los[0]}]
set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[1]}] set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[1]}]
set_property -dict {LOC AM9 IOSTANDARD LVCMOS18} [get_ports {sfp_rx_los[1]}]
# 156.25 MHz MGT reference clock # 156.25 MHz MGT reference clock
create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]

6
src/eth/example/KCU105/fpga/rtl/fpga.sv
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@@ -83,7 +83,8 @@ module fpga #
input wire logic sfp_mgt_refclk_0_p, input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n, input wire logic sfp_mgt_refclk_0_n,
output wire logic [1:0] sfp_tx_disable_b output wire logic [1:0] sfp_tx_disable_b,
input wire logic [1:0] sfp_rx_los
); );
// Clock and reset // Clock and reset
@@ -644,7 +645,8 @@ core_inst (
.sfp1_gmii_tx_en(sfp1_gmii_tx_en_int), .sfp1_gmii_tx_en(sfp1_gmii_tx_en_int),
.sfp1_gmii_tx_er(sfp1_gmii_tx_er_int), .sfp1_gmii_tx_er(sfp1_gmii_tx_er_int),
.sfp_tx_disable_b(sfp_tx_disable_b) .sfp_tx_disable_b(sfp_tx_disable_b),
.sfp_rx_los(sfp_rx_los)
); );
endmodule endmodule

3
src/eth/example/KCU105/fpga/rtl/fpga_core.sv
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@@ -106,7 +106,8 @@ module fpga_core #
output wire logic sfp1_gmii_tx_en, output wire logic sfp1_gmii_tx_en,
output wire logic sfp1_gmii_tx_er, output wire logic sfp1_gmii_tx_er,
output wire logic [1:0] sfp_tx_disable_b output wire logic [1:0] sfp_tx_disable_b,
input wire logic [1:0] sfp_rx_los
); );
assign led = sw; assign led = sw;