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lss: Add UART module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-03 15:02:48 -08:00
parent 8aa4c066b2
commit c4558a02f0
7 changed files with 676 additions and 0 deletions
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4
rtl/lss/taxi_uart.f Normal file
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taxi_uart.sv
taxi_uart_rx.sv
taxi_uart_tx.sv
../axis/taxi_axis_if.sv

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rtl/lss/taxi_uart.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART
*/
module taxi_uart #
(
parameter DATA_W = 8
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
/*
* UART interface
*/
input wire logic rxd,
output wire logic txd,
/*
* Status
*/
output wire logic tx_busy,
output wire logic rx_busy,
output wire logic rx_overrun_error,
output wire logic rx_frame_error,
/*
* Configuration
*/
input wire logic [15:0] prescale
);
taxi_uart_tx #(
.DATA_W(DATA_W)
)
uart_tx_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis_tx(s_axis_tx),
/*
* UART interface
*/
.txd(txd),
/*
* Status
*/
.busy(tx_busy),
/*
* Configuration
*/
.prescale(prescale)
);
taxi_uart_rx #(
.DATA_W(DATA_W)
)
uart_rx_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream output (source)
*/
.m_axis_rx(m_axis_rx),
/*
* UART interface
*/
.rxd(rxd),
/*
* Status
*/
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
/*
* Configuration
*/
.prescale(prescale)
);
endmodule
`resetall

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rtl/lss/taxi_uart_rx.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART (RX)
*/
module taxi_uart_rx #
(
parameter DATA_W = 8
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
/*
* UART interface
*/
input wire logic rxd,
/*
* Status
*/
output wire logic busy,
output wire logic overrun_error,
output wire logic frame_error,
/*
* Configuration
*/
input wire logic [15:0] prescale
);
// check configuration
if (m_axis_rx.DATA_W != DATA_W)
$fatal(0, "Error: Interface parameter DATA_W mismatch (instance %m)");
logic [DATA_W-1:0] m_axis_tdata_reg = 0;
logic m_axis_tvalid_reg = 0;
logic rxd_reg = 1;
logic busy_reg = 0;
logic overrun_error_reg = 0;
logic frame_error_reg = 0;
logic [DATA_W-1:0] data_reg = 0;
logic [18:0] prescale_reg = 0;
logic [3:0] bit_cnt_reg = 0;
assign m_axis_rx.tdata = m_axis_tdata_reg;
assign m_axis_rx.tkeep = 1'b1;
assign m_axis_rx.tstrb = m_axis_rx.tkeep;
assign m_axis_rx.tvalid = m_axis_tvalid_reg;
assign m_axis_rx.tlast = 1'b1;
assign busy = busy_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always_ff @(posedge clk) begin
rxd_reg <= rxd;
overrun_error_reg <= 0;
frame_error_reg <= 0;
if (m_axis_rx.tvalid && m_axis_rx.tready) begin
m_axis_tvalid_reg <= 0;
end
if (prescale_reg > 0) begin
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt_reg > 0) begin
if (bit_cnt_reg > DATA_W+1) begin
if (!rxd_reg) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
end else begin
bit_cnt_reg <= 0;
prescale_reg <= 0;
end
end else if (bit_cnt_reg > 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
data_reg <= {rxd_reg, data_reg[DATA_W-1:1]};
end else if (bit_cnt_reg == 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
if (rxd_reg) begin
m_axis_tdata_reg <= data_reg;
m_axis_tvalid_reg <= 1;
overrun_error_reg <= m_axis_tvalid_reg;
end else begin
frame_error_reg <= 1;
end
end
end else begin
busy_reg <= 0;
if (!rxd_reg) begin
prescale_reg <= {prescale, 2'd0}-2;
bit_cnt_reg <= DATA_W+2;
data_reg <= 0;
busy_reg <= 1;
end
end
if (rst) begin
m_axis_tdata_reg <= 0;
m_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0;
bit_cnt_reg <= 0;
busy_reg <= 0;
overrun_error_reg <= 0;
frame_error_reg <= 0;
end
end
endmodule
`resetall

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rtl/lss/taxi_uart_tx.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART (TX)
*/
module taxi_uart_tx #
(
parameter DATA_W = 8
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
/*
* UART interface
*/
output wire logic txd,
/*
* Status
*/
output wire logic busy,
/*
* Configuration
*/
input wire logic [15:0] prescale
);
// check configuration
if (s_axis_tx.DATA_W != DATA_W)
$fatal(0, "Error: Interface parameter DATA_W mismatch (instance %m)");
logic s_axis_tready_reg = 0;
logic txd_reg = 1;
logic busy_reg = 0;
logic [DATA_W:0] data_reg = 0;
logic [18:0] prescale_reg = 0;
logic [3:0] bit_cnt_reg = 0;
assign s_axis_tx.tready = s_axis_tready_reg;
assign txd = txd_reg;
assign busy = busy_reg;
always_ff @(posedge clk) begin
if (prescale_reg > 0) begin
s_axis_tready_reg <= 0;
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt_reg == 0) begin
s_axis_tready_reg <= 1;
busy_reg <= 0;
if (s_axis_tx.tvalid) begin
s_axis_tready_reg <= !s_axis_tready_reg;
prescale_reg <= {prescale, 3'd0}-1;
bit_cnt_reg <= DATA_W+1;
data_reg <= {1'b1, s_axis_tx.tdata};
txd_reg <= 0;
busy_reg <= 1;
end
end else begin
if (bit_cnt_reg > 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
{data_reg, txd_reg} <= {1'b0, data_reg};
end else if (bit_cnt_reg == 1) begin
bit_cnt_reg <= bit_cnt_reg - 1;
prescale_reg <= {prescale, 3'd0}-1;
txd_reg <= 1;
end
end
if (rst) begin
s_axis_tready_reg <= 0;
txd_reg <= 1;
prescale_reg <= 0;
bit_cnt_reg <= 0;
busy_reg <= 0;
end
end
endmodule
`resetall