From c525b2893166c782336d1fe1613c81e24b84d7f6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 10 Aug 2026 00:03:53 -0700 Subject: [PATCH] eth: Update example designs Signed-off-by: Alex Forencich --- .../example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv | 31 ++++++++-------- .../fpga/tb/fpga_core/test_fpga_core.py | 4 +-- src/eth/example/VCU108/fpga/rtl/fpga_core.sv | 35 ++++++++----------- .../fpga/tb/fpga_core/test_fpga_core.py | 4 +-- 4 files changed, 34 insertions(+), 40 deletions(-) diff --git a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv index 0593fde..42bb1a1 100644 --- a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv +++ b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv @@ -270,17 +270,16 @@ assign qsfp_modsell = 1'b0; assign qsfp_resetl = 1'b1; assign qsfp_lpmode = 1'b0; -wire qsfp_tx_clk[4]; -wire qsfp_tx_rst[4]; -wire qsfp_rx_clk[4]; -wire qsfp_rx_rst[4]; +wire qsfp_tx_clk[MAC_CNT]; +wire qsfp_tx_rst[MAC_CNT]; +wire qsfp_rx_clk[MAC_CNT]; +wire qsfp_rx_rst[MAC_CNT]; -wire qsfp_rx_status[4]; +wire qsfp_rx_status[MAC_CNT]; -assign led[0] = qsfp_rx_status[0]; -assign led[1] = qsfp_rx_status[1]; -assign led[2] = qsfp_rx_status[2]; -assign led[3] = qsfp_rx_status[3]; +for (genvar n = 0; n < MAC_CNT; n = n + 1) begin + assign led[n] = qsfp_rx_status[n]; +end wire qsfp_gtpowergood; @@ -363,7 +362,7 @@ if (MAC_DATA_W == 512) begin: mac .VENDOR(VENDOR), .FAMILY(FAMILY), - .CNT(4), + .GT_CNT(4), // GT config .CFG_LOW_LATENCY(CFG_LOW_LATENCY), @@ -422,12 +421,12 @@ if (MAC_DATA_W == 512) begin: mac /* * MAC clocks */ - .rx_clk(qsfp_rx_clk), - .rx_rst_in('{4{1'b0}}), - .rx_rst_out(qsfp_rx_rst), - .tx_clk(qsfp_tx_clk), - .tx_rst_in('{4{1'b0}}), - .tx_rst_out(qsfp_tx_rst), + .rx_clk(qsfp_rx_clk[0]), + .rx_rst_in(1'b0), + .rx_rst_out(qsfp_rx_rst[0]), + .tx_clk(qsfp_tx_clk[0]), + .tx_rst_in(1'b0), + .tx_rst_out(qsfp_tx_rst[0]), /* * Transmit interface (AXI stream) diff --git a/src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py index 61c14c1..d0a32f5 100644 --- a/src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py @@ -65,14 +65,14 @@ class TB: mac = EthMac( tx_clk=inst.ch[0].ch_inst.gt.gt_inst.gt_txoutclk, - tx_rst=inst.tx_rst_out[0], + tx_rst=inst.tx_rst_out, tx_bus=AxiStreamBus.from_entity(inst.cmac.cmac_axis_tx), # tx_ptp_time=inst.tx_ptp_ts_out, # tx_ptp_ts=inst.tx_ptp_ts, # tx_ptp_ts_tag=inst.tx_ptp_ts_tag, # tx_ptp_ts_valid=inst.tx_ptp_ts_valid, rx_clk=inst.ch[0].ch_inst.gt.gt_inst.gt_rxoutclk, - rx_rst=inst.rx_rst_out[0], + rx_rst=inst.rx_rst_out, rx_bus=AxiStreamBus.from_entity(inst.cmac.cmac_axis_rx), # rx_ptp_time=inst.rx_ptp_ts_out, ifg=12, speed=100e9 diff --git a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv index e97a99e..6ef9ae8 100644 --- a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv @@ -293,21 +293,16 @@ assign qsfp_modsell = 1'b0; assign qsfp_resetl = 1'b1; assign qsfp_lpmode = 1'b0; -wire qsfp_tx_clk[4]; -wire qsfp_tx_rst[4]; -wire qsfp_rx_clk[4]; -wire qsfp_rx_rst[4]; +wire qsfp_tx_clk[MAC_CNT]; +wire qsfp_tx_rst[MAC_CNT]; +wire qsfp_rx_clk[MAC_CNT]; +wire qsfp_rx_rst[MAC_CNT]; -wire qsfp_rx_status[4]; +wire qsfp_rx_status[MAC_CNT]; -assign led[0] = qsfp_rx_rst[0]; -assign led[1] = qsfp_rx_rst[1]; -assign led[2] = qsfp_rx_rst[2]; -assign led[3] = qsfp_rx_rst[3]; -assign led[4] = qsfp_rx_status[0]; -assign led[5] = qsfp_rx_status[1]; -assign led[6] = qsfp_rx_status[2]; -assign led[7] = qsfp_rx_status[3]; +for (genvar n = 0; n < MAC_CNT; n = n + 1) begin + assign led[n] = qsfp_rx_status[n]; +end wire qsfp_gtpowergood; @@ -390,7 +385,7 @@ if (MAC_DATA_W == 512) begin: mac .VENDOR(VENDOR), .FAMILY(FAMILY), - .CNT(4), + .GT_CNT(4), // GT config .CFG_LOW_LATENCY(CFG_LOW_LATENCY), @@ -449,12 +444,12 @@ if (MAC_DATA_W == 512) begin: mac /* * MAC clocks */ - .rx_clk(qsfp_rx_clk), - .rx_rst_in('{4{1'b0}}), - .rx_rst_out(qsfp_rx_rst), - .tx_clk(qsfp_tx_clk), - .tx_rst_in('{4{1'b0}}), - .tx_rst_out(qsfp_tx_rst), + .rx_clk(qsfp_rx_clk[0]), + .rx_rst_in(1'b0), + .rx_rst_out(qsfp_rx_rst[0]), + .tx_clk(qsfp_tx_clk[0]), + .tx_rst_in(1'b0), + .tx_rst_out(qsfp_tx_rst[0]), /* * Transmit interface (AXI stream) diff --git a/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py index c2f8c01..152897f 100644 --- a/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py @@ -68,14 +68,14 @@ class TB: mac = EthMac( tx_clk=inst.ch[0].ch_inst.gt.gt_inst.gt_txoutclk, - tx_rst=inst.tx_rst_out[0], + tx_rst=inst.tx_rst_out, tx_bus=AxiStreamBus.from_entity(inst.cmac.cmac_axis_tx), # tx_ptp_time=inst.tx_ptp_ts_out, # tx_ptp_ts=inst.tx_ptp_ts, # tx_ptp_ts_tag=inst.tx_ptp_ts_tag, # tx_ptp_ts_valid=inst.tx_ptp_ts_valid, rx_clk=inst.ch[0].ch_inst.gt.gt_inst.gt_rxoutclk, - rx_rst=inst.rx_rst_out[0], + rx_rst=inst.rx_rst_out, rx_bus=AxiStreamBus.from_entity(inst.cmac.cmac_axis_rx), # rx_ptp_time=inst.rx_ptp_ts_out, ifg=12, speed=100e9