diff --git a/rtl/eth/taxi_xgmii_baser_dec_64.sv b/rtl/eth/taxi_xgmii_baser_dec_64.sv new file mode 100644 index 0000000..10af0bd --- /dev/null +++ b/rtl/eth/taxi_xgmii_baser_dec_64.sv @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * XGMII 10GBASE-R decoder + */ +module taxi_xgmii_baser_dec_64 # +( + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter HDR_W = 2 +) +( + input wire logic clk, + input wire logic rst, + + /* + * 10GBASE-R encoded input + */ + input wire logic [DATA_W-1:0] encoded_rx_data, + input wire logic [HDR_W-1:0] encoded_rx_hdr, + + /* + * XGMII interface + */ + output wire logic [DATA_W-1:0] xgmii_rxd, + output wire logic [CTRL_W-1:0] xgmii_rxc, + + /* + * Status + */ + output wire logic rx_bad_block, + output wire logic rx_sequence_error +); + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64"); + +if (CTRL_W * 8 != DATA_W) + $fatal(0, "Error: Interface requires byte (8-bit) granularity"); + +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +localparam [7:0] + XGMII_IDLE = 8'h07, + XGMII_LPI = 8'h06, + XGMII_START = 8'hfb, + XGMII_TERM = 8'hfd, + XGMII_ERROR = 8'hfe, + XGMII_SEQ_OS = 8'h9c, + XGMII_RES_0 = 8'h1c, + XGMII_RES_1 = 8'h3c, + XGMII_RES_2 = 8'h7c, + XGMII_RES_3 = 8'hbc, + XGMII_RES_4 = 8'hdc, + XGMII_RES_5 = 8'hf7, + XGMII_SIG_OS = 8'h5c; + +localparam [6:0] + CTRL_IDLE = 7'h00, + CTRL_LPI = 7'h06, + CTRL_ERROR = 7'h1e, + CTRL_RES_0 = 7'h2d, + CTRL_RES_1 = 7'h33, + CTRL_RES_2 = 7'h4b, + CTRL_RES_3 = 7'h55, + CTRL_RES_4 = 7'h66, + CTRL_RES_5 = 7'h78; + +localparam [3:0] + O_SEQ_OS = 4'h0, + O_SIG_OS = 4'hf; + +localparam [1:0] + SYNC_DATA = 2'b10, + SYNC_CTRL = 2'b01; + +localparam [7:0] + BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT + BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT + BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT + BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT + BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT + BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT + BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT + BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT + BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT + BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT + BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT + BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT + BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT + BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT + BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT + +logic [DATA_W-1:0] decoded_ctrl; +logic [CTRL_W-1:0] decode_err; + +logic [DATA_W-1:0] xgmii_rxd_reg = '0, xgmii_rxd_next; +logic [CTRL_W-1:0] xgmii_rxc_reg = '0, xgmii_rxc_next; + +logic rx_bad_block_reg = 1'b0, rx_bad_block_next; +logic rx_sequence_error_reg = 1'b0, rx_sequence_error_next; +logic frame_reg = 1'b0, frame_next; + +assign xgmii_rxd = xgmii_rxd_reg; +assign xgmii_rxc = xgmii_rxc_reg; + +assign rx_bad_block = rx_bad_block_reg; +assign rx_sequence_error = rx_sequence_error_reg; + +always_comb begin + xgmii_rxd_next = {8{XGMII_ERROR}}; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = 1'b0; + rx_sequence_error_next = 1'b0; + frame_next = frame_reg; + + for (integer i = 0; i < CTRL_W; i = i + 1) begin + case (encoded_rx_data[7*i+8 +: 7]) + CTRL_IDLE: begin + decoded_ctrl[8*i +: 8] = XGMII_IDLE; + decode_err[i] = 1'b0; + end + CTRL_LPI: begin + decoded_ctrl[8*i +: 8] = XGMII_LPI; + decode_err[i] = 1'b0; + end + CTRL_ERROR: begin + decoded_ctrl[8*i +: 8] = XGMII_ERROR; + decode_err[i] = 1'b0; + end + CTRL_RES_0: begin + decoded_ctrl[8*i +: 8] = XGMII_RES_0; + decode_err[i] = 1'b0; + end + CTRL_RES_1: begin + decoded_ctrl[8*i +: 8] = XGMII_RES_1; + decode_err[i] = 1'b0; + end + CTRL_RES_2: begin + decoded_ctrl[8*i +: 8] = XGMII_RES_2; + decode_err[i] = 1'b0; + end + CTRL_RES_3: begin + decoded_ctrl[8*i +: 8] = XGMII_RES_3; + decode_err[i] = 1'b0; + end + CTRL_RES_4: begin + decoded_ctrl[8*i +: 8] = XGMII_RES_4; + decode_err[i] = 1'b0; + end + CTRL_RES_5: begin + decoded_ctrl[8*i +: 8] = XGMII_RES_5; + decode_err[i] = 1'b0; + end + default: begin + decoded_ctrl[8*i +: 8] = XGMII_ERROR; + decode_err[i] = 1'b1; + end + endcase + end + + // use only four bits of block type for reduced fanin + if (encoded_rx_hdr[0] == 0) begin + xgmii_rxd_next = encoded_rx_data; + xgmii_rxc_next = 8'h00; + rx_bad_block_next = 1'b0; + end else begin + case (encoded_rx_data[7:4]) + BLOCK_TYPE_CTRL[7:4]: begin + // C7 C6 C5 C4 C3 C2 C1 C0 BT + xgmii_rxd_next = decoded_ctrl; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = decode_err != 0; + end + BLOCK_TYPE_OS_4[7:4]: begin + // D7 D6 D5 O4 C3 C2 C1 C0 BT + xgmii_rxd_next[31:0] = decoded_ctrl[31:0]; + xgmii_rxc_next[3:0] = 4'hf; + xgmii_rxd_next[63:40] = encoded_rx_data[63:40]; + xgmii_rxc_next[7:4] = 4'h1; + if (encoded_rx_data[39:36] == O_SEQ_OS) begin + xgmii_rxd_next[39:32] = XGMII_SEQ_OS; + rx_bad_block_next = decode_err[3:0] != 0; + end else begin + xgmii_rxd_next[39:32] = XGMII_ERROR; + rx_bad_block_next = 1'b1; + end + end + BLOCK_TYPE_START_4[7:4]: begin + // D7 D6 D5 C3 C2 C1 C0 BT + xgmii_rxd_next = {encoded_rx_data[63:40], XGMII_START, decoded_ctrl[31:0]}; + xgmii_rxc_next = 8'h1f; + rx_bad_block_next = decode_err[3:0] != 0; + rx_sequence_error_next = frame_reg; + frame_next = 1'b1; + end + BLOCK_TYPE_OS_START[7:4]: begin + // D7 D6 D5 O0 D3 D2 D1 BT + xgmii_rxd_next[31:8] = encoded_rx_data[31:8]; + xgmii_rxc_next[3:0] = 4'hf; + if (encoded_rx_data[35:32] == O_SEQ_OS) begin + xgmii_rxd_next[7:0] = XGMII_SEQ_OS; + rx_bad_block_next = 1'b0; + end else begin + xgmii_rxd_next[7:0] = XGMII_ERROR; + rx_bad_block_next = 1'b1; + end + xgmii_rxd_next[63:32] = {encoded_rx_data[63:40], XGMII_START}; + xgmii_rxc_next[7:4] = 4'h1; + rx_sequence_error_next = frame_reg; + frame_next = 1'b1; + end + BLOCK_TYPE_OS_04[7:4]: begin + // D7 D6 D5 O4 O0 D3 D2 D1 BT + rx_bad_block_next = 1'b0; + xgmii_rxd_next[31:8] = encoded_rx_data[31:8]; + xgmii_rxc_next[3:0] = 4'h1; + if (encoded_rx_data[35:32] == O_SEQ_OS) begin + xgmii_rxd_next[7:0] = XGMII_SEQ_OS; + end else begin + xgmii_rxd_next[7:0] = XGMII_ERROR; + rx_bad_block_next = 1'b1; + end + xgmii_rxd_next[63:40] = encoded_rx_data[63:40]; + xgmii_rxc_next[7:4] = 4'h1; + if (encoded_rx_data[39:36] == O_SEQ_OS) begin + xgmii_rxd_next[39:32] = XGMII_SEQ_OS; + end else begin + xgmii_rxd_next[39:32] = XGMII_ERROR; + rx_bad_block_next = 1'b1; + end + end + BLOCK_TYPE_START_0[7:4]: begin + // D7 D6 D5 D4 D3 D2 D1 BT + xgmii_rxd_next = {encoded_rx_data[63:8], XGMII_START}; + xgmii_rxc_next = 8'h01; + rx_bad_block_next = 1'b0; + rx_sequence_error_next = frame_reg; + frame_next = 1'b1; + end + BLOCK_TYPE_OS_0[7:4]: begin + // C7 C6 C5 C4 O0 D3 D2 D1 BT + xgmii_rxd_next[31:8] = encoded_rx_data[31:8]; + xgmii_rxc_next[3:0] = 4'h1; + if (encoded_rx_data[35:32] == O_SEQ_OS) begin + xgmii_rxd_next[7:0] = XGMII_SEQ_OS; + rx_bad_block_next = decode_err[7:4] != 0; + end else begin + xgmii_rxd_next[7:0] = XGMII_ERROR; + rx_bad_block_next = 1'b1; + end + xgmii_rxd_next[63:32] = decoded_ctrl[63:32]; + xgmii_rxc_next[7:4] = 4'hf; + end + BLOCK_TYPE_TERM_0[7:4]: begin + // C7 C6 C5 C4 C3 C2 C1 BT + xgmii_rxd_next = {decoded_ctrl[63:8], XGMII_TERM}; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = decode_err[7:1] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_1[7:4]: begin + // C7 C6 C5 C4 C3 C2 D0 BT + xgmii_rxd_next = {decoded_ctrl[63:16], XGMII_TERM, encoded_rx_data[15:8]}; + xgmii_rxc_next = 8'hfe; + rx_bad_block_next = decode_err[7:2] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_2[7:4]: begin + // C7 C6 C5 C4 C3 D1 D0 BT + xgmii_rxd_next = {decoded_ctrl[63:24], XGMII_TERM, encoded_rx_data[23:8]}; + xgmii_rxc_next = 8'hfc; + rx_bad_block_next = decode_err[7:3] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_3[7:4]: begin + // C7 C6 C5 C4 D2 D1 D0 BT + xgmii_rxd_next = {decoded_ctrl[63:32], XGMII_TERM, encoded_rx_data[31:8]}; + xgmii_rxc_next = 8'hf8; + rx_bad_block_next = decode_err[7:4] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_4[7:4]: begin + // C7 C6 C5 D3 D2 D1 D0 BT + xgmii_rxd_next = {decoded_ctrl[63:40], XGMII_TERM, encoded_rx_data[39:8]}; + xgmii_rxc_next = 8'hf0; + rx_bad_block_next = decode_err[7:5] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_5[7:4]: begin + // C7 C6 D4 D3 D2 D1 D0 BT + xgmii_rxd_next = {decoded_ctrl[63:48], XGMII_TERM, encoded_rx_data[47:8]}; + xgmii_rxc_next = 8'he0; + rx_bad_block_next = decode_err[7:6] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_6[7:4]: begin + // C7 D5 D4 D3 D2 D1 D0 BT + xgmii_rxd_next = {decoded_ctrl[63:56], XGMII_TERM, encoded_rx_data[55:8]}; + xgmii_rxc_next = 8'hc0; + rx_bad_block_next = decode_err[7] != 0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + BLOCK_TYPE_TERM_7[7:4]: begin + // D6 D5 D4 D3 D2 D1 D0 BT + xgmii_rxd_next = {XGMII_TERM, encoded_rx_data[63:8]}; + xgmii_rxc_next = 8'h80; + rx_bad_block_next = 1'b0; + rx_sequence_error_next = !frame_reg; + frame_next = 1'b0; + end + default: begin + // invalid block type + xgmii_rxd_next = {8{XGMII_ERROR}}; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = 1'b1; + end + endcase + end + + // check all block type bits to detect bad encodings + if (encoded_rx_hdr == SYNC_DATA) begin + // data - nothing encoded + end else if (encoded_rx_hdr == SYNC_CTRL) begin + // control - check for bad block types + case (encoded_rx_data[7:0]) + BLOCK_TYPE_CTRL: begin end + BLOCK_TYPE_OS_4: begin end + BLOCK_TYPE_START_4: begin end + BLOCK_TYPE_OS_START: begin end + BLOCK_TYPE_OS_04: begin end + BLOCK_TYPE_START_0: begin end + BLOCK_TYPE_OS_0: begin end + BLOCK_TYPE_TERM_0: begin end + BLOCK_TYPE_TERM_1: begin end + BLOCK_TYPE_TERM_2: begin end + BLOCK_TYPE_TERM_3: begin end + BLOCK_TYPE_TERM_4: begin end + BLOCK_TYPE_TERM_5: begin end + BLOCK_TYPE_TERM_6: begin end + BLOCK_TYPE_TERM_7: begin end + default: begin + // invalid block type + xgmii_rxd_next = {8{XGMII_ERROR}}; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = 1'b1; + end + endcase + end else begin + // invalid header + xgmii_rxd_next = {8{XGMII_ERROR}}; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = 1'b1; + end +end + +always_ff @(posedge clk) begin + xgmii_rxd_reg <= xgmii_rxd_next; + xgmii_rxc_reg <= xgmii_rxc_next; + + rx_bad_block_reg <= rx_bad_block_next; + rx_sequence_error_reg <= rx_sequence_error_next; + frame_reg <= frame_next; + + if (rst) begin + frame_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/rtl/eth/taxi_xgmii_baser_enc_64.sv b/rtl/eth/taxi_xgmii_baser_enc_64.sv new file mode 100644 index 0000000..41de01e --- /dev/null +++ b/rtl/eth/taxi_xgmii_baser_enc_64.sv @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * XGMII 10GBASE-R encoder + */ +module taxi_xgmii_baser_enc_64 # +( + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter HDR_W = 2 +) +( + input wire logic clk, + input wire logic rst, + + /* + * XGMII interface + */ + input wire logic [DATA_W-1:0] xgmii_txd, + input wire logic [CTRL_W-1:0] xgmii_txc, + + /* + * 10GBASE-R encoded interface + */ + output wire logic [DATA_W-1:0] encoded_tx_data, + output wire logic [HDR_W-1:0] encoded_tx_hdr, + + /* + * Status + */ + output wire logic tx_bad_block +); + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64"); + +if (CTRL_W * 8 != DATA_W) + $fatal(0, "Error: Interface requires byte (8-bit) granularity"); + +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +localparam [7:0] + XGMII_IDLE = 8'h07, + XGMII_LPI = 8'h06, + XGMII_START = 8'hfb, + XGMII_TERM = 8'hfd, + XGMII_ERROR = 8'hfe, + XGMII_SEQ_OS = 8'h9c, + XGMII_RES_0 = 8'h1c, + XGMII_RES_1 = 8'h3c, + XGMII_RES_2 = 8'h7c, + XGMII_RES_3 = 8'hbc, + XGMII_RES_4 = 8'hdc, + XGMII_RES_5 = 8'hf7, + XGMII_SIG_OS = 8'h5c; + +localparam [6:0] + CTRL_IDLE = 7'h00, + CTRL_LPI = 7'h06, + CTRL_ERROR = 7'h1e, + CTRL_RES_0 = 7'h2d, + CTRL_RES_1 = 7'h33, + CTRL_RES_2 = 7'h4b, + CTRL_RES_3 = 7'h55, + CTRL_RES_4 = 7'h66, + CTRL_RES_5 = 7'h78; + +localparam [3:0] + O_SEQ_OS = 4'h0, + O_SIG_OS = 4'hf; + +localparam [1:0] + SYNC_DATA = 2'b10, + SYNC_CTRL = 2'b01; + +localparam [7:0] + BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT + BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT + BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT + BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT + BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT + BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT + BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT + BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT + BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT + BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT + BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT + BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT + BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT + BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT + BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT + +logic [DATA_W*7/8-1:0] encoded_ctrl; +logic [CTRL_W-1:0] encode_err; + +logic [DATA_W-1:0] encoded_tx_data_reg = '0, encoded_tx_data_next; +logic [HDR_W-1:0] encoded_tx_hdr_reg = '0, encoded_tx_hdr_next; + +logic tx_bad_block_reg = 1'b0, tx_bad_block_next; + +assign encoded_tx_data = encoded_tx_data_reg; +assign encoded_tx_hdr = encoded_tx_hdr_reg; + +assign tx_bad_block = tx_bad_block_reg; + +always_comb begin + tx_bad_block_next = 1'b0; + + for (integer i = 0; i < CTRL_W; i = i + 1) begin + if (xgmii_txc[i]) begin + // control + case (xgmii_txd[8*i +: 8]) + XGMII_IDLE: begin + encoded_ctrl[7*i +: 7] = CTRL_IDLE; + encode_err[i] = 1'b0; + end + XGMII_LPI: begin + encoded_ctrl[7*i +: 7] = CTRL_LPI; + encode_err[i] = 1'b0; + end + XGMII_ERROR: begin + encoded_ctrl[7*i +: 7] = CTRL_ERROR; + encode_err[i] = 1'b0; + end + XGMII_RES_0: begin + encoded_ctrl[7*i +: 7] = CTRL_RES_0; + encode_err[i] = 1'b0; + end + XGMII_RES_1: begin + encoded_ctrl[7*i +: 7] = CTRL_RES_1; + encode_err[i] = 1'b0; + end + XGMII_RES_2: begin + encoded_ctrl[7*i +: 7] = CTRL_RES_2; + encode_err[i] = 1'b0; + end + XGMII_RES_3: begin + encoded_ctrl[7*i +: 7] = CTRL_RES_3; + encode_err[i] = 1'b0; + end + XGMII_RES_4: begin + encoded_ctrl[7*i +: 7] = CTRL_RES_4; + encode_err[i] = 1'b0; + end + XGMII_RES_5: begin + encoded_ctrl[7*i +: 7] = CTRL_RES_5; + encode_err[i] = 1'b0; + end + default: begin + encoded_ctrl[7*i +: 7] = CTRL_ERROR; + encode_err[i] = 1'b1; + end + endcase + end else begin + // data (always invalid as control) + encoded_ctrl[7*i +: 7] = CTRL_ERROR; + encode_err[i] = 1'b1; + end + end + + if (xgmii_txc == 8'h00) begin + encoded_tx_data_next = xgmii_txd; + encoded_tx_hdr_next = SYNC_DATA; + tx_bad_block_next = 1'b0; + end else begin + if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_SEQ_OS) begin + // ordered set in lane 4 + encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, encoded_ctrl[27:0], BLOCK_TYPE_OS_4}; + tx_bad_block_next = encode_err[3:0] != 0; + end else if (xgmii_txc == 8'h1f && xgmii_txd[39:32] == XGMII_START) begin + // start in lane 4 + encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, encoded_ctrl[27:0], BLOCK_TYPE_START_4}; + tx_bad_block_next = encode_err[3:0] != 0; + end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_START) begin + // ordered set in lane 0, start in lane 4 + encoded_tx_data_next = {xgmii_txd[63:40], 4'd0, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_START}; + tx_bad_block_next = 1'b0; + end else if (xgmii_txc == 8'h11 && xgmii_txd[7:0] == XGMII_SEQ_OS && xgmii_txd[39:32] == XGMII_SEQ_OS) begin + // ordered set in lane 0 and lane 4 + encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_04}; + tx_bad_block_next = 1'b0; + end else if (xgmii_txc == 8'h01 && xgmii_txd[7:0] == XGMII_START) begin + // start in lane 0 + encoded_tx_data_next = {xgmii_txd[63:8], BLOCK_TYPE_START_0}; + tx_bad_block_next = 1'b0; + end else if (xgmii_txc == 8'hf1 && xgmii_txd[7:0] == XGMII_SEQ_OS) begin + // ordered set in lane 0 + encoded_tx_data_next = {encoded_ctrl[55:28], O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_OS_0}; + tx_bad_block_next = encode_err[7:4] != 0; + end else if (xgmii_txc == 8'hff && xgmii_txd[7:0] == XGMII_TERM) begin + // terminate in lane 0 + encoded_tx_data_next = {encoded_ctrl[55:7], 7'd0, BLOCK_TYPE_TERM_0}; + tx_bad_block_next = encode_err[7:1] != 0; + end else if (xgmii_txc == 8'hfe && xgmii_txd[15:8] == XGMII_TERM) begin + // terminate in lane 1 + encoded_tx_data_next = {encoded_ctrl[55:14], 6'd0, xgmii_txd[7:0], BLOCK_TYPE_TERM_1}; + tx_bad_block_next = encode_err[7:2] != 0; + end else if (xgmii_txc == 8'hfc && xgmii_txd[23:16] == XGMII_TERM) begin + // terminate in lane 2 + encoded_tx_data_next = {encoded_ctrl[55:21], 5'd0, xgmii_txd[15:0], BLOCK_TYPE_TERM_2}; + tx_bad_block_next = encode_err[7:3] != 0; + end else if (xgmii_txc == 8'hf8 && xgmii_txd[31:24] == XGMII_TERM) begin + // terminate in lane 3 + encoded_tx_data_next = {encoded_ctrl[55:28], 4'd0, xgmii_txd[23:0], BLOCK_TYPE_TERM_3}; + tx_bad_block_next = encode_err[7:4] != 0; + end else if (xgmii_txc == 8'hf0 && xgmii_txd[39:32] == XGMII_TERM) begin + // terminate in lane 4 + encoded_tx_data_next = {encoded_ctrl[55:35], 3'd0, xgmii_txd[31:0], BLOCK_TYPE_TERM_4}; + tx_bad_block_next = encode_err[7:5] != 0; + end else if (xgmii_txc == 8'he0 && xgmii_txd[47:40] == XGMII_TERM) begin + // terminate in lane 5 + encoded_tx_data_next = {encoded_ctrl[55:42], 2'd0, xgmii_txd[39:0], BLOCK_TYPE_TERM_5}; + tx_bad_block_next = encode_err[7:6] != 0; + end else if (xgmii_txc == 8'hc0 && xgmii_txd[55:48] == XGMII_TERM) begin + // terminate in lane 6 + encoded_tx_data_next = {encoded_ctrl[55:49], 1'd0, xgmii_txd[47:0], BLOCK_TYPE_TERM_6}; + tx_bad_block_next = encode_err[7] != 0; + end else if (xgmii_txc == 8'h80 && xgmii_txd[63:56] == XGMII_TERM) begin + // terminate in lane 7 + encoded_tx_data_next = {xgmii_txd[55:0], BLOCK_TYPE_TERM_7}; + tx_bad_block_next = 1'b0; + end else if (xgmii_txc == 8'hff) begin + // all control + encoded_tx_data_next = {encoded_ctrl, BLOCK_TYPE_CTRL}; + tx_bad_block_next = encode_err != 0; + end else begin + // no corresponding block format + encoded_tx_data_next = {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL}; + tx_bad_block_next = 1'b1; + end + encoded_tx_hdr_next = SYNC_CTRL; + end +end + +always_ff @(posedge clk) begin + encoded_tx_data_reg <= encoded_tx_data_next; + encoded_tx_hdr_reg <= encoded_tx_hdr_next; + + tx_bad_block_reg <= tx_bad_block_next; +end + +endmodule + +`resetall diff --git a/tb/eth/baser.py b/tb/eth/baser.py new file mode 100644 index 0000000..de19182 --- /dev/null +++ b/tb/eth/baser.py @@ -0,0 +1,613 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging + +import cocotb +from cocotb.queue import Queue, QueueFull +from cocotb.triggers import RisingEdge, Timer, First, Event +from cocotb.utils import get_sim_time + +from cocotbext.eth.constants import (EthPre, XgmiiCtrl, BaseRCtrl, BaseRO, + BaseRSync, BaseRBlockType, xgmii_ctrl_to_baser_mapping, + baser_ctrl_to_xgmii_mapping, block_type_term_lane_mapping) +from cocotbext.eth import XgmiiFrame + + +class BaseRSerdesSource(): + + def __init__(self, data, header, clock, enable=None, slip=None, scramble=True, reverse=False, *args, **kwargs): + self.log = logging.getLogger(f"cocotb.{data._path}") + self.data = data + self.header = header + self.clock = clock + self.enable = enable + self.slip = slip + self.scramble = scramble + self.reverse = reverse + + self.log.info("BASE-R serdes source") + self.log.info("Copyright (c) 2021 Alex Forencich") + self.log.info("https://github.com/alexforencich/verilog-ethernet") + + super().__init__(*args, **kwargs) + + self.active = False + self.queue = Queue() + self.dequeue_event = Event() + self.current_frame = None + self.idle_event = Event() + self.idle_event.set() + + self.enable_dic = True + self.ifg = 12 + self.force_offset_start = False + + self.bit_offset = 0 + + self.queue_occupancy_bytes = 0 + self.queue_occupancy_frames = 0 + + self.queue_occupancy_limit_bytes = -1 + self.queue_occupancy_limit_frames = -1 + + self.width = len(self.data) + self.byte_size = 8 + self.byte_lanes = 8 + + assert self.width == self.byte_lanes * self.byte_size + + self.log.info("BASE-R serdes source model configuration") + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info(" Enable scrambler: %s", self.scramble) + self.log.info(" Bit reverse: %s", self.reverse) + + self.data.setimmediatevalue(0) + self.header.setimmediatevalue(0) + + self._run_cr = cocotb.start_soon(self._run()) + + async def send(self, frame): + while self.full(): + self.dequeue_event.clear() + await self.dequeue_event.wait() + frame = XgmiiFrame(frame) + await self.queue.put(frame) + self.idle_event.clear() + self.queue_occupancy_bytes += len(frame) + self.queue_occupancy_frames += 1 + + def send_nowait(self, frame): + if self.full(): + raise QueueFull() + frame = XgmiiFrame(frame) + self.queue.put_nowait(frame) + self.idle_event.clear() + self.queue_occupancy_bytes += len(frame) + self.queue_occupancy_frames += 1 + + def count(self): + return self.queue.qsize() + + def empty(self): + return self.queue.empty() + + def full(self): + if self.queue_occupancy_limit_bytes > 0 and self.queue_occupancy_bytes > self.queue_occupancy_limit_bytes: + return True + elif self.queue_occupancy_limit_frames > 0 and self.queue_occupancy_frames > self.queue_occupancy_limit_frames: + return True + else: + return False + + def idle(self): + return self.empty() and not self.active + + def clear(self): + while not self.queue.empty(): + frame = self.queue.get_nowait() + frame.sim_time_end = None + frame.handle_tx_complete() + self.dequeue_event.set() + self.idle_event.set() + self.queue_occupancy_bytes = 0 + self.queue_occupancy_frames = 0 + + async def wait(self): + await self.idle_event.wait() + + async def _run(self): + frame = None + frame_offset = 0 + ifg_cnt = 0 + deficit_idle_cnt = 0 + scrambler_state = 0 + last_d = 0 + self.active = False + + while True: + await RisingEdge(self.clock) + + if self.enable is None or self.enable.value: + if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4): + # in IFG + ifg_cnt = ifg_cnt - self.byte_lanes + if ifg_cnt < 0: + if self.enable_dic: + deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0) + ifg_cnt = 0 + + elif frame is None: + # idle + if not self.queue.empty(): + # send frame + frame = self.queue.get_nowait() + self.dequeue_event.set() + self.queue_occupancy_bytes -= len(frame) + self.queue_occupancy_frames -= 1 + self.current_frame = frame + frame.sim_time_start = get_sim_time() + frame.sim_time_sfd = None + frame.sim_time_end = None + self.log.info("TX frame: %s", frame) + frame.normalize() + frame.start_lane = 0 + assert frame.data[0] == EthPre.PRE + assert frame.ctrl[0] == 0 + frame.data[0] = XgmiiCtrl.START + frame.ctrl[0] = 1 + frame.data.append(XgmiiCtrl.TERM) + frame.ctrl.append(1) + + # offset start + if self.enable_dic: + min_ifg = 3 - deficit_idle_cnt + else: + min_ifg = 0 + + if self.byte_lanes > 4 and (ifg_cnt > min_ifg or self.force_offset_start): + ifg_cnt = ifg_cnt-4 + frame.start_lane = 4 + frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data + frame.ctrl = [1]*4+frame.ctrl + + if self.enable_dic: + deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0) + ifg_cnt = 0 + self.active = True + frame_offset = 0 + else: + # clear counters + deficit_idle_cnt = 0 + ifg_cnt = 0 + + if frame is not None: + dl = bytearray() + cl = [] + + for k in range(self.byte_lanes): + if frame is not None: + d = frame.data[frame_offset] + if frame.sim_time_sfd is None and d == EthPre.SFD: + frame.sim_time_sfd = get_sim_time() + dl.append(d) + cl.append(frame.ctrl[frame_offset]) + frame_offset += 1 + + if frame_offset >= len(frame.data): + ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0) + frame.sim_time_end = get_sim_time() + frame.handle_tx_complete() + frame = None + self.current_frame = None + else: + dl.append(XgmiiCtrl.IDLE) + cl.append(1) + + # remap control characters + ctrl = sum(xgmii_ctrl_to_baser_mapping.get(d, BaseRCtrl.ERROR) << i*7 for i, d in enumerate(dl)) + + if not any(cl): + # data + header = BaseRSync.DATA + data = int.from_bytes(dl, 'little') + else: + # control + header = BaseRSync.CTRL + if cl[0] and dl[0] == XgmiiCtrl.START and not any(cl[1:]): + # start in lane 0 + data = BaseRBlockType.START_0 + for i in range(1, 8): + data |= dl[i] << i*8 + elif cl[4] and dl[4] == XgmiiCtrl.START and not any(cl[5:]): + # start in lane 4 + if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]): + # ordered set in lane 0 + data = BaseRBlockType.OS_START + for i in range(1, 4): + data |= dl[i] << i*8 + if dl[0] == XgmiiCtrl.SIG_OS: + # signal ordered set + data |= BaseRO.SIG_OS << 32 + else: + # other control + data = BaseRBlockType.START_4 | (ctrl & 0xfffffff) << 8 + + for i in range(5, 8): + data |= dl[i] << i*8 + elif cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]): + # ordered set in lane 0 + if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]): + # ordered set in lane 4 + data = BaseRBlockType.OS_04 + for i in range(5, 8): + data |= dl[i] << i*8 + if dl[4] == XgmiiCtrl.SIG_OS: + # signal ordered set + data |= BaseRO.SIG_OS << 36 + else: + data = BaseRBlockType.OS_0 | (ctrl & 0xfffffff) << 40 + for i in range(1, 4): + data |= dl[i] << i*8 + if dl[0] == XgmiiCtrl.SIG_OS: + # signal ordered set + data |= BaseRO.SIG_OS << 32 + elif cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]): + # ordered set in lane 4 + data = BaseRBlockType.OS_4 | (ctrl & 0xfffffff) << 8 + for i in range(5, 8): + data |= dl[i] << i*8 + if dl[4] == XgmiiCtrl.SIG_OS: + # signal ordered set + data |= BaseRO.SIG_OS << 36 + elif cl[0] and dl[0] == XgmiiCtrl.TERM: + # terminate in lane 0 + data = BaseRBlockType.TERM_0 | (ctrl & 0xffffffffffff80) << 8 + elif cl[1] and dl[1] == XgmiiCtrl.TERM and not cl[0]: + # terminate in lane 1 + data = BaseRBlockType.TERM_1 | (ctrl & 0xffffffffffc000) << 8 | dl[0] << 8 + elif cl[2] and dl[2] == XgmiiCtrl.TERM and not any(cl[0:2]): + # terminate in lane 2 + data = BaseRBlockType.TERM_2 | (ctrl & 0xffffffffe00000) << 8 + for i in range(2): + data |= dl[i] << ((i+1)*8) + elif cl[3] and dl[3] == XgmiiCtrl.TERM and not any(cl[0:3]): + # terminate in lane 3 + data = BaseRBlockType.TERM_3 | (ctrl & 0xfffffff0000000) << 8 + for i in range(3): + data |= dl[i] << ((i+1)*8) + elif cl[4] and dl[4] == XgmiiCtrl.TERM and not any(cl[0:4]): + # terminate in lane 4 + data = BaseRBlockType.TERM_4 | (ctrl & 0xfffff800000000) << 8 + for i in range(4): + data |= dl[i] << ((i+1)*8) + elif cl[5] and dl[5] == XgmiiCtrl.TERM and not any(cl[0:5]): + # terminate in lane 5 + data = BaseRBlockType.TERM_5 | (ctrl & 0xfffc0000000000) << 8 + for i in range(5): + data |= dl[i] << ((i+1)*8) + elif cl[6] and dl[6] == XgmiiCtrl.TERM and not any(cl[0:6]): + # terminate in lane 6 + data = BaseRBlockType.TERM_6 | (ctrl & 0xfe000000000000) << 8 + for i in range(6): + data |= dl[i] << ((i+1)*8) + elif cl[7] and dl[7] == XgmiiCtrl.TERM and not any(cl[0:7]): + # terminate in lane 7 + data = BaseRBlockType.TERM_7 + for i in range(7): + data |= dl[i] << ((i+1)*8) + else: + # all control + data = BaseRBlockType.CTRL | ctrl << 8 + else: + data = BaseRBlockType.CTRL + header = BaseRSync.CTRL + self.active = False + self.idle_event.set() + + if self.scramble: + # 64b/66b scrambler + b = 0 + for i in range(len(self.data)): + if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)): + scrambler_state = ((scrambler_state & 0x1ffffffffffffff) << 1) | 1 + b = b | (1 << i) + else: + scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 + data = b + + if self.slip is not None and self.slip.value: + self.bit_offset += 1 + + self.bit_offset = max(0, self.bit_offset) % 66 + + if self.bit_offset != 0: + d = data << 2 | header + + out_d = ((last_d | d << 66) >> 66-self.bit_offset) & 0x3ffffffffffffffff + + last_d = d + + data = out_d >> 2 + header = out_d & 3 + + if self.reverse: + # bit reverse + data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1) + header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1) + + self.data.value = data + self.header.value = header + + +class BaseRSerdesSink: + + def __init__(self, data, header, clock, enable=None, scramble=True, reverse=False, *args, **kwargs): + self.log = logging.getLogger(f"cocotb.{data._path}") + self.data = data + self.header = header + self.clock = clock + self.enable = enable + self.scramble = scramble + self.reverse = reverse + + self.log.info("BASE-R serdes sink") + self.log.info("Copyright (c) 2021 Alex Forencich") + self.log.info("https://github.com/alexforencich/verilog-ethernet") + + super().__init__(*args, **kwargs) + + self.active = False + self.queue = Queue() + self.active_event = Event() + + self.queue_occupancy_bytes = 0 + self.queue_occupancy_frames = 0 + + self.width = len(self.data) + self.byte_size = 8 + self.byte_lanes = 8 + + assert self.width == self.byte_lanes * self.byte_size + + self.log.info("BASE-R serdes sink model configuration") + self.log.info(" Byte size: %d bits", self.byte_size) + self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes) + self.log.info(" Enable scrambler: %s", self.scramble) + self.log.info(" Bit reverse: %s", self.reverse) + + self._run_cr = cocotb.start_soon(self._run()) + + def _recv(self, frame, compact=True): + if self.queue.empty(): + self.active_event.clear() + self.queue_occupancy_bytes -= len(frame) + self.queue_occupancy_frames -= 1 + if compact: + frame.compact() + return frame + + async def recv(self, compact=True): + frame = await self.queue.get() + return self._recv(frame, compact) + + def recv_nowait(self, compact=True): + frame = self.queue.get_nowait() + return self._recv(frame, compact) + + def count(self): + return self.queue.qsize() + + def empty(self): + return self.queue.empty() + + def idle(self): + return not self.active + + def clear(self): + while not self.queue.empty(): + self.queue.get_nowait() + self.active_event.clear() + self.queue_occupancy_bytes = 0 + self.queue_occupancy_frames = 0 + + async def wait(self, timeout=0, timeout_unit=None): + if not self.empty(): + return + if timeout: + await First(self.active_event.wait(), Timer(timeout, timeout_unit)) + else: + await self.active_event.wait() + + async def _run(self): + frame = None + scrambler_state = 0 + self.active = False + + while True: + await RisingEdge(self.clock) + + if self.enable is None or self.enable.value: + data = self.data.value.integer + header = self.header.value.integer + + if self.reverse: + # bit reverse + data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1) + header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1) + + if self.scramble: + # 64b/66b descrambler + b = 0 + for i in range(len(self.data)): + if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)): + b = b | (1 << i) + scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 | bool(data & (1 << i)) + data = b + + # 10GBASE-R decoding + + # remap control characters + ctrl = bytearray(baser_ctrl_to_xgmii_mapping.get((data >> i*7+8) & 0x7f, XgmiiCtrl.ERROR) for i in range(8)) + + data = data.to_bytes(8, 'little') + + dl = bytearray() + cl = [] + if header == BaseRSync.DATA: + # data + dl = data + cl = [0]*8 + elif header == BaseRSync.CTRL: + if data[0] == BaseRBlockType.CTRL: + # C7 C6 C5 C4 C3 C2 C1 C0 BT + dl = ctrl + cl = [1]*8 + elif data[0] == BaseRBlockType.OS_4: + # D7 D6 D5 O4 C3 C2 C1 C0 BT + dl = ctrl[0:4] + cl = [1]*4 + if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS: + dl.append(XgmiiCtrl.SEQ_OS) + elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS: + dl.append(XgmiiCtrl.SIG_OS) + else: + dl.append(XgmiiCtrl.ERROR) + cl.append(1) + dl += data[5:] + cl += [0]*3 + elif data[0] == BaseRBlockType.START_4: + # D7 D6 D5 C3 C2 C1 C0 BT + dl = ctrl[0:4] + cl = [1]*4 + dl.append(XgmiiCtrl.START) + cl.append(1) + dl += data[5:] + cl += [0]*3 + elif data[0] == BaseRBlockType.OS_START: + # D7 D6 D5 O0 D3 D2 D1 BT + if data[4] & 0xf == BaseRO.SEQ_OS: + dl.append(XgmiiCtrl.SEQ_OS) + elif data[4] & 0xf == BaseRO.SIG_OS: + dl.append(XgmiiCtrl.SIG_OS) + else: + dl.append(XgmiiCtrl.ERROR) + cl.append(1) + dl += data[1:4] + cl += [0]*3 + dl.append(XgmiiCtrl.START) + cl.append(1) + dl += data[5:] + cl += [0]*3 + elif data[0] == BaseRBlockType.OS_04: + # D7 D6 D5 O4 O0 D3 D2 D1 BT + if data[4] & 0xf == BaseRO.SEQ_OS: + dl.append(XgmiiCtrl.SEQ_OS) + elif data[4] & 0xf == BaseRO.SIG_OS: + dl.append(XgmiiCtrl.SIG_OS) + else: + dl.append(XgmiiCtrl.ERROR) + cl.append(1) + dl += data[1:4] + cl += [0]*3 + if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS: + dl.append(XgmiiCtrl.SEQ_OS) + elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS: + dl.append(XgmiiCtrl.SIG_OS) + else: + dl.append(XgmiiCtrl.ERROR) + cl.append(1) + dl += data[5:] + cl += [0]*3 + elif data[0] == BaseRBlockType.START_0: + # D7 D6 D5 D4 D3 D2 D1 BT + dl.append(XgmiiCtrl.START) + cl.append(1) + dl += data[1:] + cl += [0]*7 + elif data[0] == BaseRBlockType.OS_0: + # C7 C6 C5 C4 O0 D3 D2 D1 BT + if data[4] & 0xf == BaseRO.SEQ_OS: + dl.append(XgmiiCtrl.SEQ_OS) + elif data[4] & 0xf == BaseRO.SIG_OS: + dl.append(XgmiiCtrl.SEQ_OS) + else: + dl.append(XgmiiCtrl.ERROR) + cl.append(1) + dl += data[1:4] + cl += [0]*3 + dl += ctrl[4:] + cl += [1]*4 + elif data[0] in {BaseRBlockType.TERM_0, BaseRBlockType.TERM_1, + BaseRBlockType.TERM_2, BaseRBlockType.TERM_3, BaseRBlockType.TERM_4, + BaseRBlockType.TERM_5, BaseRBlockType.TERM_6, BaseRBlockType.TERM_7}: + # C7 C6 C5 C4 C3 C2 C1 BT + # C7 C6 C5 C4 C3 C2 D0 BT + # C7 C6 C5 C4 C3 D1 D0 BT + # C7 C6 C5 C4 D2 D1 D0 BT + # C7 C6 C5 D3 D2 D1 D0 BT + # C7 C6 D4 D3 D2 D1 D0 BT + # C7 D5 D4 D3 D2 D1 D0 BT + # D6 D5 D4 D3 D2 D1 D0 BT + term_lane = block_type_term_lane_mapping[data[0]] + dl += data[1:term_lane+1] + cl += [0]*term_lane + dl.append(XgmiiCtrl.TERM) + cl.append(1) + dl += ctrl[term_lane+1:] + cl += [1]*(7-term_lane) + else: + # invalid block type + self.log.warning("Invalid block type") + dl = [XgmiiCtrl.ERROR]*8 + cl = [1]*8 + else: + # invalid sync header + self.log.warning("Invalid sync header") + dl = [XgmiiCtrl.ERROR]*8 + cl = [1]*8 + + for offset in range(self.byte_lanes): + d_val = dl[offset] + c_val = cl[offset] + + if frame is None: + if c_val and d_val == XgmiiCtrl.START: + # start + frame = XgmiiFrame(bytearray([EthPre.PRE]), [0]) + frame.sim_time_start = get_sim_time() + frame.start_lane = offset + else: + if c_val: + # got a control character; terminate frame reception + if d_val != XgmiiCtrl.TERM: + # store control character if it's not a termination + frame.data.append(d_val) + frame.ctrl.append(c_val) + + frame.compact() + frame.sim_time_end = get_sim_time() + self.log.info("RX frame: %s", frame) + + self.queue_occupancy_bytes += len(frame) + self.queue_occupancy_frames += 1 + + self.queue.put_nowait(frame) + self.active_event.set() + + frame = None + else: + if frame.sim_time_sfd is None and d_val == EthPre.SFD: + frame.sim_time_sfd = get_sim_time() + + frame.data.append(d_val) + frame.ctrl.append(c_val) diff --git a/tb/eth/taxi_xgmii_baser_dec_64/Makefile b/tb/eth/taxi_xgmii_baser_dec_64/Makefile new file mode 100644 index 0000000..5aba5af --- /dev/null +++ b/tb/eth/taxi_xgmii_baser_dec_64/Makefile @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps +export COCOTB_RESOLVE_X ?= RANDOM + +DUT = taxi_xgmii_baser_dec_64 +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 64 +export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_HDR_W := 2 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/tb/eth/taxi_xgmii_baser_dec_64/baser.py b/tb/eth/taxi_xgmii_baser_dec_64/baser.py new file mode 120000 index 0000000..33a2368 --- /dev/null +++ b/tb/eth/taxi_xgmii_baser_dec_64/baser.py @@ -0,0 +1 @@ +../baser.py \ No newline at end of file diff --git a/tb/eth/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py b/tb/eth/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py new file mode 100644 index 0000000..ce2e2b9 --- /dev/null +++ b/tb/eth/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py @@ -0,0 +1,243 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import sys + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.eth import XgmiiSink, XgmiiFrame + +try: + from baser import BaseRSerdesSource +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + + self.source = BaseRSerdesSource(dut.encoded_rx_data, dut.encoded_rx_hdr, dut.clk, scramble=False) + self.sink = XgmiiSink(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True, + force_offset_start=False): + + tb = TB(dut) + + tb.source.ifg = ifg + tb.source.enable_dic = enable_dic + tb.source.force_offset_start = force_offset_start + + await tb.reset() + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data) + await tb.source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True, + force_offset_start=False): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + + tb.source.ifg = ifg + tb.source.enable_dic = enable_dic + tb.source.force_offset_start = force_offset_start + + for length in range(60, 92): + + await tb.reset() + + test_frames = [payload_data(length) for k in range(10)] + start_lane = [] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data) + await tb.source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.ctrl is None + + start_lane.append(rx_frame.start_lane) + + tb.log.info("length: %d", length) + tb.log.info("start_lane: %s", start_lane) + + start_lane_ref = [] + + # compute expected starting lanes + lane = 0 + deficit_idle_count = 0 + + for test_data in test_frames: + if ifg == 0: + lane = 0 + if force_offset_start and byte_lanes > 4: + lane = 4 + + start_lane_ref.append(lane) + lane = (lane + len(test_data)+4+ifg) % byte_lanes + + if enable_dic: + offset = lane % 4 + if deficit_idle_count+offset >= 4: + offset += 4 + lane = (lane - offset) % byte_lanes + deficit_idle_count = (deficit_idle_count + offset) % 4 + else: + offset = lane % 4 + if offset > 0: + offset += 4 + lane = (lane - offset) % byte_lanes + + tb.log.info("start_lane_ref: %s", start_lane_ref) + + assert start_lane_ref == start_lane + + await RisingEdge(dut.clk) + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.add_option("enable_dic", [True, False]) + factory.add_option("force_offset_start", [False, True]) + factory.generate_tests() + + factory = TestFactory(run_test_alignment) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.add_option("enable_dic", [True, False]) + factory.add_option("force_offset_start", [False, True]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_xgmii_baser_dec_64(request): + dut = "taxi_xgmii_baser_dec_64" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, "eth", f"{dut}.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = 64 + parameters['CTRL_W'] = parameters['DATA_W'] // 8 + parameters['HDR_W'] = 2 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/eth/taxi_xgmii_baser_enc_64/Makefile b/tb/eth/taxi_xgmii_baser_enc_64/Makefile new file mode 100644 index 0000000..26fd6e2 --- /dev/null +++ b/tb/eth/taxi_xgmii_baser_enc_64/Makefile @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps +export COCOTB_RESOLVE_X ?= RANDOM + +DUT = taxi_xgmii_baser_enc_64 +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 64 +export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_HDR_W := 2 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/eth/taxi_xgmii_baser_enc_64/baser.py b/tb/eth/taxi_xgmii_baser_enc_64/baser.py new file mode 120000 index 0000000..33a2368 --- /dev/null +++ b/tb/eth/taxi_xgmii_baser_enc_64/baser.py @@ -0,0 +1 @@ +../baser.py \ No newline at end of file diff --git a/tb/eth/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py b/tb/eth/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py new file mode 100644 index 0000000..4aea435 --- /dev/null +++ b/tb/eth/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py @@ -0,0 +1,243 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import sys + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.eth import XgmiiSource, XgmiiFrame + +try: + from baser import BaseRSerdesSink +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSink + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + + self.source = XgmiiSource(dut.xgmii_txd, dut.xgmii_txc, dut.clk, dut.rst) + self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True, + force_offset_start=False): + + tb = TB(dut) + + tb.source.ifg = ifg + tb.source.enable_dic = enable_dic + tb.source.force_offset_start = force_offset_start + + await tb.reset() + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data) + await tb.source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True, + force_offset_start=False): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + + tb.source.ifg = ifg + tb.source.enable_dic = enable_dic + tb.source.force_offset_start = force_offset_start + + for length in range(60, 92): + + await tb.reset() + + test_frames = [payload_data(length) for k in range(10)] + start_lane = [] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data) + await tb.source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + assert rx_frame.ctrl is None + + start_lane.append(rx_frame.start_lane) + + tb.log.info("length: %d", length) + tb.log.info("start_lane: %s", start_lane) + + start_lane_ref = [] + + # compute expected starting lanes + lane = 0 + deficit_idle_count = 0 + + for test_data in test_frames: + if ifg == 0: + lane = 0 + if force_offset_start and byte_lanes > 4: + lane = 4 + + start_lane_ref.append(lane) + lane = (lane + len(test_data)+4+ifg) % byte_lanes + + if enable_dic: + offset = lane % 4 + if deficit_idle_count+offset >= 4: + offset += 4 + lane = (lane - offset) % byte_lanes + deficit_idle_count = (deficit_idle_count + offset) % 4 + else: + offset = lane % 4 + if offset > 0: + offset += 4 + lane = (lane - offset) % byte_lanes + + tb.log.info("start_lane_ref: %s", start_lane_ref) + + assert start_lane_ref == start_lane + + await RisingEdge(dut.clk) + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.add_option("enable_dic", [True, False]) + factory.add_option("force_offset_start", [False, True]) + factory.generate_tests() + + factory = TestFactory(run_test_alignment) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.add_option("enable_dic", [True, False]) + factory.add_option("force_offset_start", [False, True]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_xgmii_baser_enc_64(request): + dut = "taxi_xgmii_baser_enc_64" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, "eth", f"{dut}.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = 64 + parameters['CTRL_W'] = parameters['DATA_W'] // 8 + parameters['HDR_W'] = 2 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )