diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile index 7a92539..6e1001e 100644 --- a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile @@ -38,10 +38,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile index dfd2e8e..dbd6683 100644 --- a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile @@ -38,10 +38,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile index baf9e78..84a0d39 100644 --- a/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile @@ -37,10 +37,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile index da75cdd..f7780cb 100644 --- a/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile @@ -37,10 +37,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile index 5e6e5d8..9943e5b 100644 --- a/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile @@ -41,7 +41,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile index 85bd9b7..1235992 100644 --- a/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile @@ -41,7 +41,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile index b9e110f..72bad1b 100644 --- a/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile @@ -40,7 +40,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_vu13p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_vu13p/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_vu13p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile index 8949799..6a4dec6 100644 --- a/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile +++ b/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile @@ -40,7 +40,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration -# CONFIG_TCL_FILES = ./config.tcl +CONFIG_TCL_FILES = ./config.tcl include ../common/vivado.mk diff --git a/src/eth/example/HTG9200/fpga/fpga_vu9p/config.tcl b/src/eth/example/HTG9200/fpga/fpga_vu9p/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_vu9p/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga.sv b/src/eth/example/HTG9200/fpga/rtl/fpga.sv index 3e5b55b..cb2e9a6 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga.sv @@ -17,9 +17,16 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", - parameter string FAMILY = "virtexuplus" + // device family + parameter string FAMILY = "virtexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -172,12 +179,12 @@ wire mmcm_clkfb; IBUFGDS #( .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") + .IBUF_LOW_PWR("FALSE") ) ref_clk_ibufg_inst ( .O (ref_clk_ibufg), .I (ref_clk_p), - .IB (ref_clk_n) + .IB (ref_clk_n) ); // MMCM instance @@ -407,7 +414,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv index 6dcc1d2..1bbe8b3 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv @@ -17,9 +17,16 @@ Authors: */ module fpga # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", - parameter string FAMILY = "virtexuplus" + // device family + parameter string FAMILY = "virtexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -257,12 +264,12 @@ wire mmcm_clkfb; IBUFGDS #( .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") + .IBUF_LOW_PWR("FALSE") ) ref_clk_ibufg_inst ( .O (ref_clk_ibufg), .I (ref_clk_p), - .IB (ref_clk_n) + .IB (ref_clk_n) ); // MMCM instance @@ -553,7 +560,10 @@ fpga_core #( .PORT_CNT(PORT_CNT), .GTY_QUAD_CNT(GTY_QUAD_CNT), .GTY_CNT(GTY_CNT), - .GTY_CLK_CNT(GTY_CLK_CNT) + .GTY_CLK_CNT(GTY_CLK_CNT), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index d92a90b..2b4ac02 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -17,13 +17,21 @@ Authors: */ module fpga_core # ( + // simulation (set to avoid vendor primitives) parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", + // device family parameter string FAMILY = "virtexuplus", + // Board configuration parameter PORT_CNT = 9, parameter GTY_QUAD_CNT = PORT_CNT, parameter GTY_CNT = GTY_QUAD_CNT*4, - parameter GTY_CLK_CNT = GTY_QUAD_CNT + parameter GTY_CLK_CNT = GTY_QUAD_CNT, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 ) ( /* @@ -291,12 +299,12 @@ assign eth_port_resetl = {PORT_CNT{~eth_reset}}; wire eth_gty_tx_clk[GTY_CNT]; wire eth_gty_tx_rst[GTY_CNT]; -taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT](); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT](); wire eth_gty_rx_clk[GTY_CNT]; wire eth_gty_rx_rst[GTY_CNT]; -taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT](); wire eth_gty_rx_status[GTY_CNT]; @@ -381,12 +389,14 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad .CNT(CNT), // GT config - .CFG_LOW_LATENCY(1), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), // GT type .GT_TYPE("GTY"), - // PHY parameters + // MAC/PHY config + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .DATA_W(MAC_DATA_W), .PADDING_EN(1'b1), .DIC_EN(1'b1), .MIN_FRAME_LEN(64), diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile b/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile index eac873b..5bf00a9 100644 --- a/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile @@ -48,6 +48,9 @@ export PARAM_PORT_CNT := 9 export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT) export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) ))) export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT) +export PARAM_CFG_LOW_LATENCY := "1'b1" +export PARAM_COMBINED_MAC_PCS := "1'b1" +export PARAM_MAC_DATA_W := "64" ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py index 6be81a7..9b581fa 100644 --- a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py @@ -13,12 +13,13 @@ import logging import os import sys +import pytest import cocotb_test.simulator import cocotb from cocotb.log import SimLog from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, Timer, Combine +from cocotb.triggers import RisingEdge, Combine from cocotbext.eth import XgmiiFrame from cocotbext.uart import UartSource, UartSink @@ -56,12 +57,20 @@ class TB: for ch in inst.mac_inst.ch: gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) + else: + clk = 2.56 + gbx_cfg = None else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) @@ -119,6 +128,8 @@ async def mac_test(tb, source, sink): for k in range(1200): await RisingEdge(tb.dut.clk_125mhz) + sink.clear() + tb.log.info("Multiple small packets") count = 64 @@ -197,7 +208,8 @@ def process_f_files(files): return list(lst.values()) -def test_fpga_core(request): +@pytest.mark.parametrize("mac_data_w", [32, 64]) +def test_fpga_core(request, mac_data_w): dut = "fpga_core" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -227,6 +239,9 @@ def test_fpga_core(request): parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT'] parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4 parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT'] + parameters['CFG_LOW_LATENCY'] = "1'b1" + parameters['COMBINED_MAC_PCS'] = "1'b1" + parameters['MAC_DATA_W'] = mac_data_w extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}