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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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48
example/Alveo/fpga/README.md
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@@ -6,31 +6,41 @@ This example design targets the Xilinx Alveo series.
The design places looped-back MACs on the Ethernet ports as well as a looped-back UART on on the USB UART connections.
* USB UART
* Looped-back UART
* DSFP/QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
* USB UART
* Looped-back UART
* DSFP/QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
## Board details
* FPGA
* AU45N/SN1000: xcu26-vsva1365-2LV-e
* AU50: xcu50-fsvh2104-2-e
* AU55C: xcu55c-fsvh2892-2L-e
* AU55N/C1100: xcu55n-fsvh2892-2L-e
* AU200: xcu200-fsgd2104-2-e
* AU250: xcu250-fsgd2104-2-e
* AU280: xcu280-fsvh2892-2L-e
* VCU1525: xcvu9p-fsgd2104-2L-e
* X3/X3522: xcux35-vsva1365-3-e
* 25GBASE-R PHY: Soft PCS with GTY transceivers
* FPGA
* AU45N/SN1000: xcu26-vsva1365-2LV-e
* AU50: xcu50-fsvh2104-2-e
* AU55C: xcu55c-fsvh2892-2L-e
* AU55N/C1100: xcu55n-fsvh2892-2L-e
* AU200: xcu200-fsgd2104-2-e
* AU250: xcu250-fsgd2104-2-e
* AU280: xcu280-fsvh2892-2L-e
* VCU1525: xcvu9p-fsgd2104-2L-e
* X3/X3522: xcux35-vsva1365-3-e
* USB UART
* AU45N/SN1000: FTDI FT4232H (DMB-2)
* AU50: FTDI FT4232H (3 via DMB-1)
* AU55C: FTDI FT4232H (2 onboard, all 3 via DMB-1)
* AU55N/C1100: FTDI FT4232H (2 onboard, all 3 via DMB-1)
* AU200: FTDI FT4232H
* AU250: FTDI FT4232H
* AU280: FTDI FT4232H
* VCU1525: FTDI FT4232H
* X3/X3522: FTDI FT4232H (DMB-2)
* 25GBASE-R PHY: Soft PCS with GTY transceivers
## Licensing
* Toolchain
* Vivado Standard (enterprise license not required)
* IP
* No licensed vendor IP or 3rd party IP
* Toolchain
* Vivado Standard (enterprise license not required)
* IP
* No licensed vendor IP or 3rd party IP
## How to build

6
example/Alveo/fpga/fpga_au200.xdc
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@@ -75,9 +75,9 @@ set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
set_false_path -from [get_ports {sw[*]}]
set_input_delay 0 [get_ports {sw[*]}]
# UART
set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
# UART (U27 FT4232H channel CDBUS)
set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U27.39 CDBUS1 RXD
set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U27.38 CDBUS0 TXD
set_false_path -to [get_ports {uart_txd}]
set_output_delay 0 [get_ports {uart_txd}]

6
example/Alveo/fpga/fpga_au280.xdc
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@@ -52,9 +52,9 @@ set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset]
set_false_path -from [get_ports {reset}]
set_input_delay 0 [get_ports {reset}]
# UART
set_property -dict {LOC B33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC A28 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
# UART (U34 FT4232H channel CDBUS)
set_property -dict {LOC B33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.39 CDBUS1 RXD
set_property -dict {LOC A28 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.38 CDBUS0 TXD
set_false_path -to [get_ports {uart_txd}]
set_output_delay 0 [get_ports {uart_txd}]

6
example/Alveo/fpga/fpga_au45n.xdc
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@@ -54,9 +54,9 @@ set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
# UART
set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
# UART (DMB-2 FT4232H channel CDBUS)
set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# DMB-2 U4.39 RXD CDBUS1
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# DMB-2 U4.38 TXD CDBUS0
set_false_path -to [get_ports {uart_txd}]
set_output_delay 0 [get_ports {uart_txd}]

14
example/Alveo/fpga/fpga_au50.xdc
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@@ -44,13 +44,13 @@ set_property -dict {LOC F17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qs
set_false_path -to [get_ports {qsfp_led_act qsfp_led_stat_g qsfp_led_stat_y}]
set_output_delay 0 [get_ports {qsfp_led_act qsfp_led_stat_g qsfp_led_stat_y}]
# UART
set_property -dict {LOC BE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}]
set_property -dict {LOC BF26 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}]
set_property -dict {LOC A17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}]
set_property -dict {LOC B15 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}]
set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}]
set_property -dict {LOC A18 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}]
# UART (DMB-1 FT4232H)
set_property -dict {LOC BE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}] ;# DMB-1 U9.39 CDBUS1 RXD
set_property -dict {LOC BF26 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}] ;# DMB-1 U9.38 CDBUS0 TXD
set_property -dict {LOC A17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}] ;# DMB-1 U9.52 DDBUS1 RXD
set_property -dict {LOC B15 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}] ;# DMB-1 U9.48 DDBUS0 TXD
set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}] ;# DMB-1 U18.39 CDBUS1 RXD
set_property -dict {LOC A18 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}] ;# DMB-1 U18.38 CDBUS0 TXD
set_false_path -to [get_ports {uart_txd[*]}]
set_output_delay 0 [get_ports {uart_txd[*]}]

14
example/Alveo/fpga/fpga_au55.xdc
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@@ -59,13 +59,13 @@ set_property -dict {LOC BL12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
# UART
set_property -dict {LOC BJ41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}]
set_property -dict {LOC BK41 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}]
set_property -dict {LOC BN47 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}]
set_property -dict {LOC BP47 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}]
set_property -dict {LOC BL45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}]
set_property -dict {LOC BL46 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}]
# UART (U35 FT4232H/DMB-1 FT4232H)
set_property -dict {LOC BJ41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}] ;# U35.39 CDBUS1 RXD / DMB-1 U9.39 CDBUS1 RXD
set_property -dict {LOC BK41 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}] ;# U35.38 CDBUS0 TXD / DMB-1 U9.38 CDBUS0 TXD
set_property -dict {LOC BN47 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}] ;# U35.52 DDBUS1 RXD / DMB-1 U9.52 DDBUS1 RXD
set_property -dict {LOC BP47 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}] ;# U35.48 DDBUS0 TXD / DMB-1 U9.48 DDBUS0 TXD
set_property -dict {LOC BL45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}] ;# DMB-1 U18.39 CDBUS1 RXD
set_property -dict {LOC BL46 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}] ;# DMB-1 U18.38 CDBUS0 TXD
set_false_path -to [get_ports {uart_txd[*]}]
set_output_delay 0 [get_ports {uart_txd[*]}]

6
example/Alveo/fpga/fpga_x3522.xdc
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@@ -61,9 +61,9 @@ set_output_delay 0 [get_ports {dsfp_led_r[*] dsfp_led_g[*] dsfp_led_b[*]}]
#set_false_path -to [get_ports {pps_out}]
#set_output_delay 0 [get_ports {pps_out}]
# UART
set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
# UART (DMB-2 FT4232H channel CDBUS)
set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# DMB-2 U4.39 RXD CDBUS1
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# DMB-2 U4.38 TXD CDBUS0
set_false_path -to [get_ports {uart_txd}]
set_output_delay 0 [get_ports {uart_txd}]

1
example/Arty/fpga/README.md
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@@ -14,6 +14,7 @@ The design places a looped-back MAC on the BASE-T port, as well as a looped-back
## Board details
* FPGA: XC7A35TICSG324-1L
* USB UART: FTDI FT2232H
* PHY: TI DP83848J via MII
## Licensing

8
example/Arty/fpga/fpga.xdc
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@@ -42,6 +42,7 @@ set_false_path -to [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r
set_output_delay 0 [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}]
# Reset button
# Note: IC8.43 BDBUS4 DTR drives FPGA pin C2 (reset_n) via JP2
set_property -dict {LOC C2 IOSTANDARD LVCMOS33} [get_ports reset_n]
set_false_path -from [get_ports {reset_n}]
@@ -103,9 +104,10 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_property -dict {LOC H2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd9}] ;# PMOD JD pin 9
#set_property -dict {LOC G2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd10}] ;# PMOD JD pin 10
# UART
set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd]
set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
# UART (IC8 FT2232H BDBUS)
# Note: IC8.43 BDBUS4 DTR drives FPGA pin C2 (reset_n) via JP2
set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd] ;# IC8.39 BDBUS1 RXD
set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports uart_rxd] ;# IC8.38 BDBUS0 TXD
set_false_path -to [get_ports {uart_txd}]
set_output_delay 0 [get_ports {uart_txd}]

1
example/HTG940/fpga/README.md
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@@ -14,6 +14,7 @@ The design places a looped-back MAC on the BASE-T port, as well as a looped-back
## Board details
* FPGA: xcvu9p-flgb2104-2-e
* USB UART: Silicon Labs CP2103
* 1000BASE-T PHY: TI DP83867IRPAP via RGMII
## Licensing

12
example/HTG940/fpga/fpga.xdc
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@@ -64,12 +64,12 @@ set_property -dict {LOC BC33 IOSTANDARD LVCMOS12} [get_ports {sw[7]}]
set_false_path -from [get_ports {sw[*]}]
set_input_delay 0 [get_ports {sw[*]}]
# UART
set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports uart_txd]
set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rxd]
set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports uart_rts]
set_property -dict {LOC D14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts]
set_property -dict {LOC P16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rst_n]
# UART (U53 CP2103)
set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports {uart_txd}] ;# U53.25 TXD_O
set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rxd}] ;# U53.24 RXD_I
set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U53.23 RTS_O_B
set_property -dict {LOC D14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U53.22 CTS_I_B
set_property -dict {LOC P16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rst_n}] ;# U53.9 RST_B
set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}]
set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}]

1
example/KC705/fpga/README.md
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@@ -18,6 +18,7 @@ The design places looped-back MACs on both the BASE-T port as well as the SFP+ c
## Board details
* FPGA: XC7K325T-2FFG900C
* USB UART: Silicon Labs CP2103
* 1000BASE-T PHY: Marvell 88E1111 via GMII, RGMII, or SGMII
* 1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver

18
example/KC705/fpga/fpga.xdc
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@@ -68,16 +68,16 @@ set_property -dict {LOC Y28 IOSTANDARD LVCMOS25} [get_ports {sw[3]}] ;# from SW
set_false_path -from [get_ports {sw[*]}]
set_input_delay 0 [get_ports {sw[*]}]
# UART
set_property -dict {LOC K24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports uart_txd]
set_property -dict {LOC M19 IOSTANDARD LVCMOS25} [get_ports uart_rxd]
set_property -dict {LOC L27 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports uart_rts]
set_property -dict {LOC K23 IOSTANDARD LVCMOS25} [get_ports uart_cts]
# UART (U12 CP2103)
set_property -dict {LOC K24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U12.24 RXD_I
set_property -dict {LOC M19 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U12.25 TXD_O
set_property -dict {LOC L27 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U12.23 RTS_O_B
set_property -dict {LOC K23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U12.22 CTS_I_B
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
#set_property -dict {LOC K21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

14
example/KC705/fpga/rtl/fpga.sv
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@@ -55,8 +55,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: SFP+
@@ -251,7 +251,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -259,8 +259,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
wire [7:0] led_int;
@@ -658,8 +658,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-X SFP

6
example/KC705/fpga/rtl/fpga_core.sv
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@@ -55,8 +55,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-X SFP
@@ -106,7 +106,7 @@ module fpga_core #
assign led = sw;
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();

1
example/KCU105/fpga/README.md
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@@ -17,6 +17,7 @@ The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as
## Board details
* FPGA: xcku040-ffva1156-2-e
* USB UART: Silicon Labs CP2105 SCI
* 1000BASE-T PHY: Marvell 88E1111 via SGMII
* 1000BASE-X PHY: Xilinx PCS/PMA core via GTH transceiver
* 10GBASE-R PHY: Soft PCS with GTH transceiver

18
example/KCU105/fpga/fpga.xdc
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@@ -109,16 +109,16 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts]
set_property -dict {LOC K27 IOSTANDARD LVCMOS18} [get_ports uart_cts]
# UART (U34 CP2105 SCI)
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
set_property -dict {LOC L23 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
set_property -dict {LOC K27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
#set_property -dict {LOC J24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

14
example/KCU105/fpga/rtl/fpga.sv
View File

@@ -51,8 +51,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -236,7 +236,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -244,8 +244,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
wire [7:0] led_int;
@@ -570,8 +570,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-T SGMII

6
example/KCU105/fpga/rtl/fpga_core.sv
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@@ -50,8 +50,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T
@@ -104,7 +104,7 @@ module fpga_core #
assign led = sw;
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();

1
example/VCU108/fpga/README.md
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@@ -16,6 +16,7 @@ The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a l
## Board details
* FPGA: xcvu095-ffva2104-2-e
* USB UART: Silicon Labs CP2105 SCI
* 1000BASE-T PHY: Marvell 88E1111 via SGMII
* 25GBASE-R PHY: Soft PCS with GTY transceivers

18
example/VCU108/fpga/fpga.xdc
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@@ -106,16 +106,16 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC BE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC BC24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
set_property -dict {LOC BF24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts]
set_property -dict {LOC BD22 IOSTANDARD LVCMOS18} [get_ports uart_cts]
# UART (U34 CP2105 SCI)
set_property -dict {LOC BE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
set_property -dict {LOC BC24 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
set_property -dict {LOC BF24 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
set_property -dict {LOC BD22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
#set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

14
example/VCU108/fpga/rtl/fpga.sv
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@@ -46,8 +46,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -228,7 +228,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -236,8 +236,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// SGMII interface to PHY
@@ -377,8 +377,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-T SGMII

6
example/VCU108/fpga/rtl/fpga_core.sv
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@@ -45,8 +45,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -86,7 +86,7 @@ module fpga_core #
// assign led = 8'(sw);
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();

1
example/VCU118/fpga/README.md
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@@ -16,6 +16,7 @@ The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a l
## Board details
* FPGA: xcvu9p-flga2104-2L-e
* USB UART: Silicon Labs CP2105 SCI
* 1000BASE-T PHY: TI DP83867ISRGZ via SGMII
* 25GBASE-R PHY: Soft PCS with GTY transceivers

18
example/VCU118/fpga/fpga.xdc
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@@ -112,16 +112,16 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}]
set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}]
set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rts}]
set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {uart_cts}]
# UART (U34 CP2105 SCI)
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
set_property -dict {LOC BB22 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
set_property -dict {LOC AY25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# Gigabit Ethernet SGMII PHY
set_property -dict {LOC AU24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {phy_sgmii_rx_p}]

14
example/VCU118/fpga/rtl/fpga.sv
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@@ -52,8 +52,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -252,7 +252,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -260,8 +260,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// SI570 I2C
@@ -466,8 +466,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-T SGMII

6
example/VCU118/fpga/rtl/fpga_core.sv
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@@ -45,8 +45,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -106,7 +106,7 @@ module fpga_core #
// assign led = 8'(sw);
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();

1
example/ZCU102/fpga/README.md
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@@ -14,6 +14,7 @@ The design places looped-back MACs on the SFP+ ports as well as a looped-back UA
## Board details
* FPGA: xczu9eg-ffvb1156-2-e
* USB UART: Silicon Labs CP2108
* 10GBASE-R PHY: Soft PCS with GTH transceivers
## Licensing

11
example/ZCU102/fpga/fpga.xdc
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@@ -101,18 +101,17 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {proto_gpio[*]}]
#set_output_delay 0 [get_ports {proto_gpio[*]}]
# UART
set_property -dict {LOC F13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
set_property -dict {LOC D12 IOSTANDARD LVCMOS33} [get_ports uart_rts]
set_property -dict {LOC E12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
# UART (U40 CP2108 ch 2)
set_property -dict {LOC F13 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U40.15 RX_2
set_property -dict {LOC E13 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U40.16 TX_2
set_property -dict {LOC D12 IOSTANDARD LVCMOS12} [get_ports uart_rts] ;# U40.14 RTS_2
set_property -dict {LOC E12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_cts] ;# U40.13 CTS_2
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interfaces
#set_property -dict {LOC J10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_scl]
#set_property -dict {LOC J11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_sda]

1
example/ZCU106/fpga/README.md
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@@ -14,6 +14,7 @@ The design places looped-back MACs on the SFP+ ports as well as a looped-back UA
## Board details
* FPGA: xczu7ev-ffvc1156-2-e
* USB UART: Silicon Labs CP2108
* 10GBASE-R PHY: Soft PCS with GTH transceivers
## Licensing

10
example/ZCU106/fpga/fpga.xdc
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@@ -101,11 +101,11 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {proto_gpio[*]}]
#set_output_delay 0 [get_ports {proto_gpio[*]}]
# UART
set_property -dict {LOC AL17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC AH17 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
set_property -dict {LOC AM15 IOSTANDARD LVCMOS12} [get_ports uart_rts]
set_property -dict {LOC AP17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_cts]
# UART (U40 CP2108 ch 2)
set_property -dict {LOC AL17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U40.15 RX_2
set_property -dict {LOC AH17 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U40.16 TX_2
set_property -dict {LOC AM15 IOSTANDARD LVCMOS12} [get_ports uart_rts] ;# U40.14 RTS_2
set_property -dict {LOC AP17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_cts] ;# U40.13 CTS_2
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]

23
example/ZCU111/fpga/README.md
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@@ -6,22 +6,23 @@ This example design targets the Xilinx ZCU111 FPGA board.
The design places looped-back MACs on the SFP+ ports as well as a looped-back UART on on the USB UART connection.
* USB UART
* Looped-back UART
* QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
* USB UART
* Looped-back UART
* QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
## Board details
* FPGA: xczu28dr-ffvg1517-2-e
* 25GBASE-R PHY: Soft PCS with GTY transceivers
* FPGA: xczu28dr-ffvg1517-2-e
* USB UART: FTDI FT4232H
* 25GBASE-R PHY: Soft PCS with GTY transceivers
## Licensing
* Toolchain
* Vivado Enterprise (requires license)
* IP
* No licensed vendor IP or 3rd party IP
* Toolchain
* Vivado Enterprise (requires license)
* IP
* No licensed vendor IP or 3rd party IP
## How to build
@@ -33,7 +34,7 @@ For correct operation, several DIP switches need to be set correctly.
DIP switch settings:
* SW6: all ON (select JTAG boot)
* SW6: all ON (select JTAG boot)
## How to test

10
example/ZCU111/fpga/fpga.xdc
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@@ -91,11 +91,11 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC AU15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports uart_rts]
set_property -dict {LOC AT14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts]
# USB UART (U34 FT4232H CDBUS)
set_property -dict {LOC AU15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U34.39 CDBUS1 RXD
set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# U34.38 CDBUS0 TXD
set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports uart_rts] ;# U34.40 CDBUS2 RTS#
set_property -dict {LOC AT14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts] ;# U34.41 CDBUS3 CTS#
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]