example: Clean up and annotate USB UART connections

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-09 17:08:38 -08:00 · 2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
--- a/example/Alveo/fpga/README.md
+++ b/example/Alveo/fpga/README.md
@@ -6,31 +6,41 @@ This example design targets the Xilinx Alveo series.

 The design places looped-back MACs on the Ethernet ports as well as a looped-back UART on on the USB UART connections.

-* USB UART
-  * Looped-back UART
-* DSFP/QSFP28
-  * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
+*  USB UART
+    *  Looped-back UART
+*  DSFP/QSFP28
+    *  Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers

 ## Board details

-* FPGA
-  * AU45N/SN1000: xcu26-vsva1365-2LV-e
-  * AU50: xcu50-fsvh2104-2-e
-  * AU55C: xcu55c-fsvh2892-2L-e
-  * AU55N/C1100: xcu55n-fsvh2892-2L-e
-  * AU200: xcu200-fsgd2104-2-e
-  * AU250: xcu250-fsgd2104-2-e
-  * AU280: xcu280-fsvh2892-2L-e
-  * VCU1525: xcvu9p-fsgd2104-2L-e
-  * X3/X3522: xcux35-vsva1365-3-e
-* 25GBASE-R PHY: Soft PCS with GTY transceivers
+*  FPGA
+   *  AU45N/SN1000: xcu26-vsva1365-2LV-e
+   *  AU50: xcu50-fsvh2104-2-e
+   *  AU55C: xcu55c-fsvh2892-2L-e
+   *  AU55N/C1100: xcu55n-fsvh2892-2L-e
+   *  AU200: xcu200-fsgd2104-2-e
+   *  AU250: xcu250-fsgd2104-2-e
+   *  AU280: xcu280-fsvh2892-2L-e
+   *  VCU1525: xcvu9p-fsgd2104-2L-e
+   *  X3/X3522: xcux35-vsva1365-3-e
+*  USB UART
+   *  AU45N/SN1000: FTDI FT4232H (DMB-2)
+   *  AU50: FTDI FT4232H (3 via DMB-1)
+   *  AU55C: FTDI FT4232H (2 onboard, all 3 via DMB-1)
+   *  AU55N/C1100: FTDI FT4232H (2 onboard, all 3 via DMB-1)
+   *  AU200: FTDI FT4232H
+   *  AU250: FTDI FT4232H
+   *  AU280: FTDI FT4232H
+   *  VCU1525: FTDI FT4232H
+   *  X3/X3522: FTDI FT4232H (DMB-2)
+*  25GBASE-R PHY: Soft PCS with GTY transceivers

 ## Licensing

-* Toolchain
-  * Vivado Standard (enterprise license not required)
-* IP
-  * No licensed vendor IP or 3rd party IP
+*  Toolchain
+    *  Vivado Standard (enterprise license not required)
+*  IP
+    *  No licensed vendor IP or 3rd party IP

 ## How to build

--- a/example/Alveo/fpga/fpga_au200.xdc
+++ b/example/Alveo/fpga/fpga_au200.xdc
@@ -75,9 +75,9 @@ set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
 set_false_path -from [get_ports {sw[*]}]
 set_input_delay 0 [get_ports {sw[*]}]

-# UART
-set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd]
-set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
+# UART (U27 FT4232H channel CDBUS)
+set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U27.39 CDBUS1 RXD
+set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U27.38 CDBUS0 TXD

 set_false_path -to [get_ports {uart_txd}]
 set_output_delay 0 [get_ports {uart_txd}]
--- a/example/Alveo/fpga/fpga_au280.xdc
+++ b/example/Alveo/fpga/fpga_au280.xdc
@@ -52,9 +52,9 @@ set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset]
 set_false_path -from [get_ports {reset}]
 set_input_delay 0 [get_ports {reset}]

-# UART
-set_property -dict {LOC B33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
-set_property -dict {LOC A28 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
+# UART (U34 FT4232H channel CDBUS)
+set_property -dict {LOC B33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.39 CDBUS1 RXD
+set_property -dict {LOC A28 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.38 CDBUS0 TXD

 set_false_path -to [get_ports {uart_txd}]
 set_output_delay 0 [get_ports {uart_txd}]
--- a/example/Alveo/fpga/fpga_au45n.xdc
+++ b/example/Alveo/fpga/fpga_au45n.xdc
@@ -54,9 +54,9 @@ set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
 set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
 set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]

-# UART
-set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
-set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
+# UART (DMB-2 FT4232H channel CDBUS)
+set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# DMB-2 U4.39 RXD CDBUS1
+set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# DMB-2 U4.38 TXD CDBUS0

 set_false_path -to [get_ports {uart_txd}]
 set_output_delay 0 [get_ports {uart_txd}]
--- a/example/Alveo/fpga/fpga_au50.xdc
+++ b/example/Alveo/fpga/fpga_au50.xdc
@@ -44,13 +44,13 @@ set_property -dict {LOC F17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qs
 set_false_path -to [get_ports {qsfp_led_act qsfp_led_stat_g qsfp_led_stat_y}]
 set_output_delay 0 [get_ports {qsfp_led_act qsfp_led_stat_g qsfp_led_stat_y}]

-# UART
-set_property -dict {LOC BE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}]
-set_property -dict {LOC BF26 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}]
-set_property -dict {LOC A17  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}]
-set_property -dict {LOC B15  IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}]
-set_property -dict {LOC A19  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}]
-set_property -dict {LOC A18  IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}]
+# UART (DMB-1 FT4232H)
+set_property -dict {LOC BE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}] ;# DMB-1 U9.39 CDBUS1 RXD
+set_property -dict {LOC BF26 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}] ;# DMB-1 U9.38 CDBUS0 TXD
+set_property -dict {LOC A17  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}] ;# DMB-1 U9.52 DDBUS1 RXD
+set_property -dict {LOC B15  IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}] ;# DMB-1 U9.48 DDBUS0 TXD
+set_property -dict {LOC A19  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}] ;# DMB-1 U18.39 CDBUS1 RXD
+set_property -dict {LOC A18  IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}] ;# DMB-1 U18.38 CDBUS0 TXD

 set_false_path -to [get_ports {uart_txd[*]}]
 set_output_delay 0 [get_ports {uart_txd[*]}]
--- a/example/Alveo/fpga/fpga_au55.xdc
+++ b/example/Alveo/fpga/fpga_au55.xdc
@@ -59,13 +59,13 @@ set_property -dict {LOC BL12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
 set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
 set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]

-# UART
-set_property -dict {LOC BJ41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}]
-set_property -dict {LOC BK41 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}]
-set_property -dict {LOC BN47 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}]
-set_property -dict {LOC BP47 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}]
-set_property -dict {LOC BL45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}]
-set_property -dict {LOC BL46 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}]
+# UART (U35 FT4232H/DMB-1 FT4232H)
+set_property -dict {LOC BJ41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}] ;# U35.39 CDBUS1 RXD / DMB-1 U9.39 CDBUS1 RXD
+set_property -dict {LOC BK41 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}] ;# U35.38 CDBUS0 TXD / DMB-1 U9.38 CDBUS0 TXD
+set_property -dict {LOC BN47 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}] ;# U35.52 DDBUS1 RXD / DMB-1 U9.52 DDBUS1 RXD
+set_property -dict {LOC BP47 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}] ;# U35.48 DDBUS0 TXD / DMB-1 U9.48 DDBUS0 TXD
+set_property -dict {LOC BL45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}] ;# DMB-1 U18.39 CDBUS1 RXD
+set_property -dict {LOC BL46 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}] ;# DMB-1 U18.38 CDBUS0 TXD

 set_false_path -to [get_ports {uart_txd[*]}]
 set_output_delay 0 [get_ports {uart_txd[*]}]
--- a/example/Alveo/fpga/fpga_x3522.xdc
+++ b/example/Alveo/fpga/fpga_x3522.xdc
@@ -61,9 +61,9 @@ set_output_delay 0 [get_ports {dsfp_led_r[*] dsfp_led_g[*] dsfp_led_b[*]}]
 #set_false_path -to [get_ports {pps_out}]
 #set_output_delay 0 [get_ports {pps_out}]

-# UART
-set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
-set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
+# UART (DMB-2 FT4232H channel CDBUS)
+set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# DMB-2 U4.39 RXD CDBUS1
+set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# DMB-2 U4.38 TXD CDBUS0

 set_false_path -to [get_ports {uart_txd}]
 set_output_delay 0 [get_ports {uart_txd}]