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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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example/Alveo/fpga/README.md
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@@ -6,31 +6,41 @@ This example design targets the Xilinx Alveo series.
The design places looped-back MACs on the Ethernet ports as well as a looped-back UART on on the USB UART connections.
* USB UART
* Looped-back UART
* DSFP/QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
* USB UART
* Looped-back UART
* DSFP/QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
## Board details
* FPGA
* AU45N/SN1000: xcu26-vsva1365-2LV-e
* AU50: xcu50-fsvh2104-2-e
* AU55C: xcu55c-fsvh2892-2L-e
* AU55N/C1100: xcu55n-fsvh2892-2L-e
* AU200: xcu200-fsgd2104-2-e
* AU250: xcu250-fsgd2104-2-e
* AU280: xcu280-fsvh2892-2L-e
* VCU1525: xcvu9p-fsgd2104-2L-e
* X3/X3522: xcux35-vsva1365-3-e
* 25GBASE-R PHY: Soft PCS with GTY transceivers
* FPGA
* AU45N/SN1000: xcu26-vsva1365-2LV-e
* AU50: xcu50-fsvh2104-2-e
* AU55C: xcu55c-fsvh2892-2L-e
* AU55N/C1100: xcu55n-fsvh2892-2L-e
* AU200: xcu200-fsgd2104-2-e
* AU250: xcu250-fsgd2104-2-e
* AU280: xcu280-fsvh2892-2L-e
* VCU1525: xcvu9p-fsgd2104-2L-e
* X3/X3522: xcux35-vsva1365-3-e
* USB UART
* AU45N/SN1000: FTDI FT4232H (DMB-2)
* AU50: FTDI FT4232H (3 via DMB-1)
* AU55C: FTDI FT4232H (2 onboard, all 3 via DMB-1)
* AU55N/C1100: FTDI FT4232H (2 onboard, all 3 via DMB-1)
* AU200: FTDI FT4232H
* AU250: FTDI FT4232H
* AU280: FTDI FT4232H
* VCU1525: FTDI FT4232H
* X3/X3522: FTDI FT4232H (DMB-2)
* 25GBASE-R PHY: Soft PCS with GTY transceivers
## Licensing
* Toolchain
* Vivado Standard (enterprise license not required)
* IP
* No licensed vendor IP or 3rd party IP
* Toolchain
* Vivado Standard (enterprise license not required)
* IP
* No licensed vendor IP or 3rd party IP
## How to build