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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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example/Arty/fpga/README.md
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@@ -14,6 +14,7 @@ The design places a looped-back MAC on the BASE-T port, as well as a looped-back
## Board details
* FPGA: XC7A35TICSG324-1L
* USB UART: FTDI FT2232H
* PHY: TI DP83848J via MII
## Licensing