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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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1
example/KC705/fpga/README.md
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@@ -18,6 +18,7 @@ The design places looped-back MACs on both the BASE-T port as well as the SFP+ c
## Board details
* FPGA: XC7K325T-2FFG900C
* USB UART: Silicon Labs CP2103
* 1000BASE-T PHY: Marvell 88E1111 via GMII, RGMII, or SGMII
* 1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver

18
example/KC705/fpga/fpga.xdc
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@@ -68,16 +68,16 @@ set_property -dict {LOC Y28 IOSTANDARD LVCMOS25} [get_ports {sw[3]}] ;# from SW
set_false_path -from [get_ports {sw[*]}]
set_input_delay 0 [get_ports {sw[*]}]
# UART
set_property -dict {LOC K24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports uart_txd]
set_property -dict {LOC M19 IOSTANDARD LVCMOS25} [get_ports uart_rxd]
set_property -dict {LOC L27 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports uart_rts]
set_property -dict {LOC K23 IOSTANDARD LVCMOS25} [get_ports uart_cts]
# UART (U12 CP2103)
set_property -dict {LOC K24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U12.24 RXD_I
set_property -dict {LOC M19 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U12.25 TXD_O
set_property -dict {LOC L27 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U12.23 RTS_O_B
set_property -dict {LOC K23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U12.22 CTS_I_B
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
#set_property -dict {LOC K21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

14
example/KC705/fpga/rtl/fpga.sv
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@@ -55,8 +55,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: SFP+
@@ -251,7 +251,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -259,8 +259,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
wire [7:0] led_int;
@@ -658,8 +658,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-X SFP

6
example/KC705/fpga/rtl/fpga_core.sv
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@@ -55,8 +55,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-X SFP
@@ -106,7 +106,7 @@ module fpga_core #
assign led = sw;
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();