bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 17:08:38 -08:00
Code Issues Packages Projects Releases Wiki Activity

example: Clean up and annotate USB UART connections

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
example/KCU105/fpga/README.md
View File

@@ -17,6 +17,7 @@ The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as
## Board details
* FPGA: xcku040-ffva1156-2-e
* USB UART: Silicon Labs CP2105 SCI
* 1000BASE-T PHY: Marvell 88E1111 via SGMII
* 1000BASE-X PHY: Xilinx PCS/PMA core via GTH transceiver
* 10GBASE-R PHY: Soft PCS with GTH transceiver

18
example/KCU105/fpga/fpga.xdc
View File

@@ -109,16 +109,16 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts]
set_property -dict {LOC K27 IOSTANDARD LVCMOS18} [get_ports uart_cts]
# UART (U34 CP2105 SCI)
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
set_property -dict {LOC L23 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
set_property -dict {LOC K27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
#set_property -dict {LOC J24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

14
example/KCU105/fpga/rtl/fpga.sv
View File

@@ -51,8 +51,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -236,7 +236,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -244,8 +244,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
wire [7:0] led_int;
@@ -570,8 +570,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-T SGMII

6
example/KCU105/fpga/rtl/fpga_core.sv
View File

@@ -50,8 +50,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T
@@ -104,7 +104,7 @@ module fpga_core #
assign led = sw;
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();