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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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1
example/VCU108/fpga/README.md
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@@ -16,6 +16,7 @@ The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a l
## Board details
* FPGA: xcvu095-ffva2104-2-e
* USB UART: Silicon Labs CP2105 SCI
* 1000BASE-T PHY: Marvell 88E1111 via SGMII
* 25GBASE-R PHY: Soft PCS with GTY transceivers

18
example/VCU108/fpga/fpga.xdc
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@@ -106,16 +106,16 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC BE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC BC24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
set_property -dict {LOC BF24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts]
set_property -dict {LOC BD22 IOSTANDARD LVCMOS18} [get_ports uart_cts]
# UART (U34 CP2105 SCI)
set_property -dict {LOC BE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
set_property -dict {LOC BC24 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
set_property -dict {LOC BF24 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
set_property -dict {LOC BD22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
#set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]

14
example/VCU108/fpga/rtl/fpga.sv
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@@ -46,8 +46,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -228,7 +228,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -236,8 +236,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// SGMII interface to PHY
@@ -377,8 +377,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-T SGMII

6
example/VCU108/fpga/rtl/fpga_core.sv
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@@ -45,8 +45,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -86,7 +86,7 @@ module fpga_core #
// assign led = 8'(sw);
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();