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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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14
example/VCU108/fpga/rtl/fpga.sv
View File

@@ -46,8 +46,8 @@ module fpga #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -228,7 +228,7 @@ debounce_switch_inst (
);
wire uart_rxd_int;
wire uart_cts_int;
wire uart_rts_int;
taxi_sync_signal #(
.WIDTH(2),
@@ -236,8 +236,8 @@ taxi_sync_signal #(
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// SGMII interface to PHY
@@ -377,8 +377,8 @@ core_inst (
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: 1000BASE-T SGMII

6
example/VCU108/fpga/rtl/fpga_core.sv
View File

@@ -45,8 +45,8 @@ module fpga_core #
*/
input wire logic uart_rxd,
output wire logic uart_txd,
output wire logic uart_rts,
input wire logic uart_cts,
input wire logic uart_rts,
output wire logic uart_cts,
/*
* Ethernet: 1000BASE-T SGMII
@@ -86,7 +86,7 @@ module fpga_core #
// assign led = 8'(sw);
// UART
assign uart_rts = 0;
assign uart_cts = 1'b0;
taxi_axis_if #(.DATA_W(8)) axis_uart();