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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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18
example/VCU118/fpga/fpga.xdc
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@@ -112,16 +112,16 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}]
set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}]
set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rts}]
set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {uart_cts}]
# UART (U34 CP2105 SCI)
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
set_property -dict {LOC BB22 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
set_property -dict {LOC AY25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
set_false_path -to [get_ports {uart_txd uart_rts}]
set_output_delay 0 [get_ports {uart_txd uart_rts}]
set_false_path -from [get_ports {uart_rxd uart_cts}]
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# Gigabit Ethernet SGMII PHY
set_property -dict {LOC AU24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {phy_sgmii_rx_p}]