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example: Clean up and annotate USB UART connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-20 17:32:31 -07:00
parent 315a4715ff
commit c7cf9cc1bf
33 changed files with 177 additions and 157 deletions
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23
example/ZCU111/fpga/README.md
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@@ -6,22 +6,23 @@ This example design targets the Xilinx ZCU111 FPGA board.
The design places looped-back MACs on the SFP+ ports as well as a looped-back UART on on the USB UART connection.
* USB UART
* Looped-back UART
* QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
* USB UART
* Looped-back UART
* QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
## Board details
* FPGA: xczu28dr-ffvg1517-2-e
* 25GBASE-R PHY: Soft PCS with GTY transceivers
* FPGA: xczu28dr-ffvg1517-2-e
* USB UART: FTDI FT4232H
* 25GBASE-R PHY: Soft PCS with GTY transceivers
## Licensing
* Toolchain
* Vivado Enterprise (requires license)
* IP
* No licensed vendor IP or 3rd party IP
* Toolchain
* Vivado Enterprise (requires license)
* IP
* No licensed vendor IP or 3rd party IP
## How to build
@@ -33,7 +34,7 @@ For correct operation, several DIP switches need to be set correctly.
DIP switch settings:
* SW6: all ON (select JTAG boot)
* SW6: all ON (select JTAG boot)
## How to test

10
example/ZCU111/fpga/fpga.xdc
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@@ -91,11 +91,11 @@ set_input_delay 0 [get_ports {sw[*]}]
#set_false_path -to [get_ports {pmod1[*]}]
#set_output_delay 0 [get_ports {pmod1[*]}]
# UART
set_property -dict {LOC AU15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports uart_rts]
set_property -dict {LOC AT14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts]
# USB UART (U34 FT4232H CDBUS)
set_property -dict {LOC AU15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U34.39 CDBUS1 RXD
set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# U34.38 CDBUS0 TXD
set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports uart_rts] ;# U34.40 CDBUS2 RTS#
set_property -dict {LOC AT14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts] ;# U34.41 CDBUS3 CTS#
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]