diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index 427f774..2193317 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -171,7 +171,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // PHY parameters .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_qsfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -241,6 +242,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv b/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv index 7c81ff3..a162fb7 100644 --- a/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv +++ b/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv @@ -172,7 +172,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -242,6 +243,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{2{1'b1}}), + .an_restart('{2{1'b0}}), + .an_speedup('{2{1'b0}}), + .an_timeout_en('{2{1'b1}}), + .an_usxgmii_en('{2{1'b0}}), + .an_usxgmii_auto('{2{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{2{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index f37def9..db52c2e 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -342,7 +342,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(eth_gty_axis_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -418,6 +419,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index c1bc948..6e3b975 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -423,7 +423,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(eth_gty_axis_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -515,6 +516,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv index 51746ae..8055a95 100644 --- a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv @@ -367,7 +367,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(eth_gty_axis_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -446,6 +447,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad */ .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv index 0e463b7..ff4dd01 100644 --- a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv +++ b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv @@ -515,7 +515,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -595,6 +596,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{1{1'b1}}), + .an_restart('{1{1'b0}}), + .an_speedup('{1{1'b0}}), + .an_timeout_en('{1{1'b1}}), + .an_usxgmii_en('{1{1'b0}}), + .an_usxgmii_auto('{1{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{1{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv index d23c318..5596cd7 100644 --- a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv @@ -680,6 +680,7 @@ end else begin : sfp_mac // PHY parameters .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -756,6 +757,26 @@ end else begin : sfp_mac */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{2{1'b1}}), + .an_restart('{2{1'b0}}), + .an_speedup('{2{1'b0}}), + .an_timeout_en('{2{1'b1}}), + .an_usxgmii_en('{2{1'b0}}), + .an_usxgmii_auto('{2{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{2{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/KR260/fpga/rtl/fpga_core.sv b/src/eth/example/KR260/fpga/rtl/fpga_core.sv index 66bac14..2aa20cf 100644 --- a/src/eth/example/KR260/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KR260/fpga/rtl/fpga_core.sv @@ -416,6 +416,7 @@ end else begin : sfp_mac // PHY parameters .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -485,6 +486,26 @@ end else begin : sfp_mac */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{1{1'b1}}), + .an_restart('{1{1'b0}}), + .an_speedup('{1{1'b0}}), + .an_timeout_en('{1{1'b1}}), + .an_usxgmii_en('{1{1'b0}}), + .an_usxgmii_auto('{1{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{1{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv b/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv index 1b4ae80..047de64 100644 --- a/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv @@ -200,7 +200,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(eth_gty_axis_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -276,6 +277,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv b/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv index 52e4457..da93cf8 100644 --- a/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv @@ -157,7 +157,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -227,6 +228,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .m_axis_rx(axis_sfp_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv b/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv index 5d9dc3f..e4bcac1 100644 --- a/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv @@ -304,7 +304,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -380,6 +381,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{4{1'b1}}), + .an_restart('{4{1'b0}}), + .an_speedup('{4{1'b0}}), + .an_timeout_en('{4{1'b1}}), + .an_usxgmii_en('{4{1'b0}}), + .an_usxgmii_auto('{4{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{4{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv index 562cf20..6620d15 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv @@ -190,7 +190,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_qsfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -260,6 +261,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv index 01dd2ba..706786c 100644 --- a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv @@ -166,7 +166,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -236,6 +237,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{2{1'b1}}), + .an_restart('{2{1'b0}}), + .an_speedup('{2{1'b0}}), + .an_timeout_en('{2{1'b1}}), + .an_usxgmii_en('{2{1'b0}}), + .an_usxgmii_auto('{2{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{2{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv index 1d36978..886a32d 100644 --- a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv +++ b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv @@ -370,7 +370,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_qsfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -446,6 +447,26 @@ qsfp_mac_inst ( */ .m_axis_rx(axis_qsfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{4{1'b1}}), + .an_restart('{4{1'b0}}), + .an_speedup('{4{1'b0}}), + .an_timeout_en('{4{1'b1}}), + .an_usxgmii_en('{4{1'b0}}), + .an_usxgmii_auto('{4{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{4{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/VC709/fpga/rtl/fpga_core.sv b/src/eth/example/VC709/fpga/rtl/fpga_core.sv index 2cd157d..e0c9ca5 100644 --- a/src/eth/example/VC709/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VC709/fpga/rtl/fpga_core.sv @@ -310,6 +310,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(MAC_DATA_W), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -385,6 +386,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{4{1'b1}}), + .an_restart('{4{1'b0}}), + .an_speedup('{4{1'b0}}), + .an_timeout_en('{4{1'b1}}), + .an_usxgmii_en('{4{1'b0}}), + .an_usxgmii_auto('{4{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{4{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv index e12d1c0..116c970 100644 --- a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv @@ -397,7 +397,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_qsfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -473,6 +474,26 @@ qsfp_mac_inst ( */ .m_axis_rx(axis_qsfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{4{1'b1}}), + .an_restart('{4{1'b0}}), + .an_speedup('{4{1'b0}}), + .an_timeout_en('{4{1'b1}}), + .an_usxgmii_en('{4{1'b0}}), + .an_usxgmii_auto('{4{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{4{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv index 92c935e..f48ff21 100644 --- a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv @@ -594,7 +594,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_qsfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -670,6 +671,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv b/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv index 211feda..e95e3ee 100644 --- a/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv @@ -147,6 +147,7 @@ taxi_eth_mac_25g_us #( // PHY parameters .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -216,6 +217,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{2{1'b1}}), + .an_restart('{2{1'b0}}), + .an_speedup('{2{1'b0}}), + .an_timeout_en('{2{1'b1}}), + .an_usxgmii_en('{2{1'b0}}), + .an_usxgmii_auto('{2{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{2{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv index 3441d1d..38df216 100644 --- a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv @@ -322,6 +322,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(MAC_DATA_W), + .USXGMII_EN(1'b0), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -399,6 +400,26 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv index 9f98802..cdd166a 100644 --- a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv @@ -547,6 +547,7 @@ end else begin : sfp_mac // PHY parameters .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -622,6 +623,26 @@ end else begin : sfp_mac */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{4{1'b1}}), + .an_restart('{4{1'b0}}), + .an_speedup('{4{1'b0}}), + .an_timeout_en('{4{1'b1}}), + .an_usxgmii_en('{4{1'b0}}), + .an_usxgmii_auto('{4{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{4{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv index f7509e1..36d63b0 100644 --- a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv @@ -548,6 +548,7 @@ end else begin : sfp_mac // PHY parameters .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -624,6 +625,26 @@ end else begin : sfp_mac */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{2{1'b1}}), + .an_restart('{2{1'b0}}), + .an_speedup('{2{1'b0}}), + .an_timeout_en('{2{1'b1}}), + .an_usxgmii_en('{2{1'b0}}), + .an_usxgmii_auto('{2{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{2{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv index e99f7cd..9fbc1ca 100644 --- a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv @@ -378,7 +378,8 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_sfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -454,6 +455,26 @@ sfp_mac_inst ( */ .m_axis_rx(axis_sfp_rx), + /* + * USXGMII autonegotiation + */ + .an_en('{4{1'b1}}), + .an_restart('{4{1'b0}}), + .an_speedup('{4{1'b0}}), + .an_timeout_en('{4{1'b1}}), + .an_usxgmii_en('{4{1'b0}}), + .an_usxgmii_auto('{4{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{4{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */ diff --git a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv index da42908..9b1a765 100644 --- a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv @@ -218,7 +218,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), - .DATA_W(MAC_DATA_W), + .DATA_W(axis_qsfp_tx[0].DATA_W), + .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), @@ -288,6 +289,26 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]), + /* + * USXGMII autonegotiation + */ + .an_en('{CNT{1'b1}}), + .an_restart('{CNT{1'b0}}), + .an_speedup('{CNT{1'b0}}), + .an_timeout_en('{CNT{1'b1}}), + .an_usxgmii_en('{CNT{1'b0}}), + .an_usxgmii_auto('{CNT{1'b1}}), + .an_intr(), + .an_running(), + .an_complete(), + .an_timeout(), + .an_usxgmii_mode(), + .an_adv_ability_usxgmii('{CNT{16'h1601}}), + .an_lp_adv_ability(), + .an_lp_usxgmii_link(), + .an_lp_usxgmii_speed(), + .an_res_full_duplex(), + /* * PTP clock */