From caeacadb780b3bf01260a5154fb3bbfb707c67d8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 4 Oct 2025 20:06:58 -0700 Subject: [PATCH] eth: Clean up masking, lane 0 never needs to be masked Signed-off-by: Alex Forencich --- src/eth/rtl/taxi_axis_baser_tx_32.sv | 2 +- src/eth/rtl/taxi_axis_baser_tx_64.sv | 10 ++++------ src/eth/rtl/taxi_axis_xgmii_rx_32.sv | 15 +++++++++++---- src/eth/rtl/taxi_axis_xgmii_rx_64.sv | 4 ++-- src/eth/rtl/taxi_axis_xgmii_tx_32.sv | 4 ++-- src/eth/rtl/taxi_axis_xgmii_tx_64.sv | 4 ++-- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/src/eth/rtl/taxi_axis_baser_tx_32.sv b/src/eth/rtl/taxi_axis_baser_tx_32.sv index 3e30774..33b5ef3 100644 --- a/src/eth/rtl/taxi_axis_baser_tx_32.sv +++ b/src/eth/rtl/taxi_axis_baser_tx_32.sv @@ -298,7 +298,7 @@ endfunction wire [DATA_W-1:0] s_axis_tx_tdata_masked; for (genvar n = 0; n < KEEP_W; n = n + 1) begin - assign s_axis_tx_tdata_masked[n*8 +: 8] = s_axis_tx.tkeep[n] ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; + assign s_axis_tx_tdata_masked[n*8 +: 8] = (n == 0 || s_axis_tx.tkeep[n]) ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; end // FCS cycle calculation diff --git a/src/eth/rtl/taxi_axis_baser_tx_64.sv b/src/eth/rtl/taxi_axis_baser_tx_64.sv index ab69326..c9b01cf 100644 --- a/src/eth/rtl/taxi_axis_baser_tx_64.sv +++ b/src/eth/rtl/taxi_axis_baser_tx_64.sv @@ -179,8 +179,6 @@ logic [31:0] swap_data = 32'd0; logic output_data_finish_reg = 1'b0; -logic [DATA_W-1:0] s_axis_tx_tdata_masked; - logic [DATA_W-1:0] s_tdata_reg = '0, s_tdata_next; logic [EMPTY_W-1:0] s_empty_reg = '0, s_empty_next; @@ -314,10 +312,10 @@ function [2:0] keep2empty(input [7:0] k); endfunction // Mask input data -always_comb begin - for (integer j = 0; j < 8; j = j + 1) begin - s_axis_tx_tdata_masked[j*8 +: 8] = s_axis_tx.tkeep[j] ? s_axis_tx.tdata[j*8 +: 8] : 8'd0; - end +wire [DATA_W-1:0] s_axis_tx_tdata_masked; + +for (genvar n = 0; n < KEEP_W; n = n + 1) begin + assign s_axis_tx_tdata_masked[n*8 +: 8] = (n == 0 || s_axis_tx.tkeep[n]) ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; end // FCS cycle calculation diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv index 59f7c0c..1c1de50 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv @@ -222,6 +222,15 @@ eth_crc ( .state_out(crc_state_next) ); +// Mask input data +wire [DATA_W-1:0] xgmii_rxd_masked; +wire [CTRL_W-1:0] xgmii_term; + +for (genvar n = 0; n < CTRL_W; n = n + 1) begin + assign xgmii_rxd_masked[n*8 +: 8] = (n > 0 && xgmii_rxc[n]) ? 8'd0 : xgmii_rxd[n*8 +: 8]; + assign xgmii_term[n] = xgmii_rxc[n] && (xgmii_rxd[n*8 +: 8] == XGMII_TERM); +end + always_comb begin state_next = STATE_IDLE; @@ -529,7 +538,7 @@ always_ff @(posedge clk) begin framing_error_reg <= xgmii_rxc != 0; for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin - if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin + if (xgmii_term[i]) begin term_present_reg <= 1'b1; term_first_cycle_reg <= i == 0; term_lane_reg <= 2'(i); @@ -547,10 +556,8 @@ always_ff @(posedge clk) begin crc_valid_save <= crc_valid; - for (integer i = 0; i < CTRL_W; i = i + 1) begin - xgmii_rxd_d0[i*8 +: 8] <= xgmii_rxc[i] ? 8'd0 : xgmii_rxd[i*8 +: 8]; - end xgmii_rxc_d0 <= xgmii_rxc; + xgmii_rxd_d0 <= xgmii_rxd_masked; xgmii_rxd_d1 <= xgmii_rxd_d0; xgmii_rxd_d2 <= xgmii_rxd_d1; diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv index dbaec71..39f3a68 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv @@ -239,7 +239,7 @@ wire [DATA_W-1:0] xgmii_rxd_masked; wire [CTRL_W-1:0] xgmii_term; for (genvar n = 0; n < CTRL_W; n = n + 1) begin - assign xgmii_rxd_masked[n*8 +: 8] = xgmii_rxc[n] ? 8'd0 : xgmii_rxd[n*8 +: 8]; + assign xgmii_rxd_masked[n*8 +: 8] = (n > 0 && xgmii_rxc[n]) ? 8'd0 : xgmii_rxd[n*8 +: 8]; assign xgmii_term[n] = xgmii_rxc[n] && (xgmii_rxd[n*8 +: 8] == XGMII_TERM); end @@ -574,7 +574,7 @@ always_ff @(posedge clk) begin framing_error_reg <= xgmii_rxc != 0; for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin - if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin + if (xgmii_term[i]) begin term_present_reg <= 1'b1; term_first_cycle_reg <= i <= 4; term_lane_reg <= 3'(i); diff --git a/src/eth/rtl/taxi_axis_xgmii_tx_32.sv b/src/eth/rtl/taxi_axis_xgmii_tx_32.sv index d5b96dc..ef09bac 100644 --- a/src/eth/rtl/taxi_axis_xgmii_tx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_tx_32.sv @@ -246,8 +246,8 @@ endfunction // Mask input data wire [DATA_W-1:0] s_axis_tx_tdata_masked; -for (genvar n = 0; n < CTRL_W; n = n + 1) begin - assign s_axis_tx_tdata_masked[n*8 +: 8] = s_axis_tx.tkeep[n] ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; +for (genvar n = 0; n < KEEP_W; n = n + 1) begin + assign s_axis_tx_tdata_masked[n*8 +: 8] = (n == 0 || s_axis_tx.tkeep[n]) ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; end // FCS cycle calculation diff --git a/src/eth/rtl/taxi_axis_xgmii_tx_64.sv b/src/eth/rtl/taxi_axis_xgmii_tx_64.sv index 3157f92..2b1c9b6 100644 --- a/src/eth/rtl/taxi_axis_xgmii_tx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_tx_64.sv @@ -258,8 +258,8 @@ endfunction // Mask input data wire [DATA_W-1:0] s_axis_tx_tdata_masked; -for (genvar n = 0; n < CTRL_W; n = n + 1) begin - assign s_axis_tx_tdata_masked[n*8 +: 8] = s_axis_tx.tkeep[n] ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; +for (genvar n = 0; n < KEEP_W; n = n + 1) begin + assign s_axis_tx_tdata_masked[n*8 +: 8] = (n == 0 || s_axis_tx.tkeep[n]) ? s_axis_tx.tdata[n*8 +: 8] : 8'd0; end // FCS cycle calculation