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example/VCU118: Add example design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
529
example/VCU118/fpga/rtl/fpga.sv
Normal file
529
example/VCU118/fpga/rtl/fpga.sv
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@@ -0,0 +1,529 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Clock: 125MHz LVDS
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* Reset: Push button, active low
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*/
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input wire logic clk_125mhz_p,
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input wire logic clk_125mhz_n,
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [3:0] sw,
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output wire logic [7:0] led,
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/*
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* I2C for board management
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*/
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inout wire logic i2c_scl,
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inout wire logic i2c_sda,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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output wire logic uart_rts,
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input wire logic uart_cts,
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/*
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* Ethernet: 1000BASE-T SGMII
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*/
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input wire logic phy_sgmii_rx_p,
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input wire logic phy_sgmii_rx_n,
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output wire logic phy_sgmii_tx_p,
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output wire logic phy_sgmii_tx_n,
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input wire logic phy_sgmii_clk_p,
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input wire logic phy_sgmii_clk_n,
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output wire logic phy_reset_n,
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input wire logic phy_int_n,
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inout wire logic phy_mdio,
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output wire logic phy_mdc,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp1_tx_p,
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output wire logic [3:0] qsfp1_tx_n,
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input wire logic [3:0] qsfp1_rx_p,
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input wire logic [3:0] qsfp1_rx_n,
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input wire logic qsfp1_mgt_refclk_0_p,
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input wire logic qsfp1_mgt_refclk_0_n,
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// input wire logic qsfp1_mgt_refclk_1_p,
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// input wire logic qsfp1_mgt_refclk_1_n,
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// output wire logic qsfp1_recclk_p,
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// output wire logic qsfp1_recclk_n,
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output wire logic qsfp1_modsell,
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output wire logic qsfp1_resetl,
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input wire logic qsfp1_modprsl,
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input wire logic qsfp1_intl,
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output wire logic qsfp1_lpmode,
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output wire logic [3:0] qsfp2_tx_p,
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output wire logic [3:0] qsfp2_tx_n,
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input wire logic [3:0] qsfp2_rx_p,
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input wire logic [3:0] qsfp2_rx_n,
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// input wire logic qsfp2_mgt_refclk_0_p,
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// input wire logic qsfp2_mgt_refclk_0_n,
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// input wire logic qsfp2_mgt_refclk_1_p,
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// input wire logic qsfp2_mgt_refclk_1_n,
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// output wire logic qsfp2_recclk_p,
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// output wire logic qsfp2_recclk_n,
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output wire logic qsfp2_modsell,
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output wire logic qsfp2_resetl,
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input wire logic qsfp2_modprsl,
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input wire logic qsfp2_intl,
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output wire logic qsfp2_lpmode
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);
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// Clock and reset
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wire clk_125mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_125mhz_ibufg_inst (
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.O (clk_125mhz_ibufg),
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.I (clk_125mhz_p),
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.IB (clk_125mhz_n)
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);
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// MMCM instance
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MMCME4_BASE #(
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// 125 MHz input
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.CLKIN1_PERIOD(8.0),
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.REF_JITTER1(0.010),
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// 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 125 MHz PFD * 10 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 125 MHz input
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.CLKIN1(clk_125mhz_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_cts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_rxd, uart_cts}),
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.out({uart_rxd_int, uart_cts_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o = 1'b1;
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wire i2c_scl_t = 1'b1;
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wire i2c_sda_i;
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wire i2c_sda_o = 1'b1;
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wire i2c_sda_t = 1'b1;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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// SGMII interface to PHY
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wire phy_gmii_clk_int;
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wire phy_gmii_rst_int;
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wire phy_gmii_clk_en_int;
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wire [7:0] phy_gmii_txd_int;
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wire phy_gmii_tx_en_int;
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wire phy_gmii_tx_er_int;
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wire [7:0] phy_gmii_rxd_int;
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wire phy_gmii_rx_dv_int;
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wire phy_gmii_rx_er_int;
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wire [15:0] pcspma_status_vector;
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wire pcspma_status_link_status = pcspma_status_vector[0];
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wire pcspma_status_link_synchronization = pcspma_status_vector[1];
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wire pcspma_status_rudi_c = pcspma_status_vector[2];
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wire pcspma_status_rudi_i = pcspma_status_vector[3];
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wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
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wire pcspma_status_rxdisperr = pcspma_status_vector[5];
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wire pcspma_status_rxnotintable = pcspma_status_vector[6];
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wire pcspma_status_phy_link_status = pcspma_status_vector[7];
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wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
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wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
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wire pcspma_status_duplex = pcspma_status_vector[12];
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wire pcspma_status_remote_fault = pcspma_status_vector[13];
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wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
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wire [4:0] pcspma_config_vector;
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assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
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assign pcspma_config_vector[3] = 1'b0; // isolate
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assign pcspma_config_vector[2] = 1'b0; // power down
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assign pcspma_config_vector[1] = 1'b0; // loopback enable
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assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
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wire [15:0] pcspma_an_config_vector;
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assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
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assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
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assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
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assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
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assign pcspma_an_config_vector[9] = 1'b0; // reserved
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assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
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assign pcspma_an_config_vector[6] = 1'b0; // reserved
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assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
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assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
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assign pcspma_an_config_vector[0] = 1'b1; // SGMII
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sgmii_pcs_pma_0
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eth_pcspma (
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// SGMII
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.txp_0 (phy_sgmii_tx_p),
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.txn_0 (phy_sgmii_tx_n),
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.rxp_0 (phy_sgmii_rx_p),
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.rxn_0 (phy_sgmii_rx_n),
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// Ref clock from PHY
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.refclk625_p (phy_sgmii_clk_p),
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.refclk625_n (phy_sgmii_clk_n),
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// async reset
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.reset (rst_125mhz_int),
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// clock and reset outputs
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.clk125_out (phy_gmii_clk_int),
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.clk312_out (),
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.rst_125_out (phy_gmii_rst_int),
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.tx_logic_reset (),
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.rx_logic_reset (),
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.tx_locked (),
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.rx_locked (),
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.tx_pll_clk_out (),
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.rx_pll_clk_out (),
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// MAC clocking
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.sgmii_clk_r_0 (),
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.sgmii_clk_f_0 (),
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.sgmii_clk_en_0 (phy_gmii_clk_en_int),
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// Speed control
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.speed_is_10_100_0 (pcspma_status_speed != 2'b10),
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.speed_is_100_0 (pcspma_status_speed == 2'b01),
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// Internal GMII
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.gmii_txd_0 (phy_gmii_txd_int),
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.gmii_tx_en_0 (phy_gmii_tx_en_int),
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.gmii_tx_er_0 (phy_gmii_tx_er_int),
|
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.gmii_rxd_0 (phy_gmii_rxd_int),
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.gmii_rx_dv_0 (phy_gmii_rx_dv_int),
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.gmii_rx_er_0 (phy_gmii_rx_er_int),
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.gmii_isolate_0 (),
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// Configuration
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.configuration_vector_0 (pcspma_config_vector),
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.an_interrupt_0 (),
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.an_adv_config_vector_0 (pcspma_an_config_vector),
|
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.an_restart_config_0 (1'b0),
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// Status
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.status_vector_0 (pcspma_status_vector),
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.signal_detect_0 (1'b1),
|
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// Cascade
|
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.tx_bsc_rst_out (),
|
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.rx_bsc_rst_out (),
|
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.tx_bs_rst_out (),
|
||||
.rx_bs_rst_out (),
|
||||
.tx_rst_dly_out (),
|
||||
.rx_rst_dly_out (),
|
||||
.tx_bsc_en_vtc_out (),
|
||||
.rx_bsc_en_vtc_out (),
|
||||
.tx_bs_en_vtc_out (),
|
||||
.rx_bs_en_vtc_out (),
|
||||
.riu_clk_out (),
|
||||
.riu_addr_out (),
|
||||
.riu_wr_data_out (),
|
||||
.riu_wr_en_out (),
|
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.riu_nibble_sel_out (),
|
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.riu_rddata_1 (16'b0),
|
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.riu_valid_1 (1'b0),
|
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.riu_prsnt_1 (1'b0),
|
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.riu_rddata_2 (16'b0),
|
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.riu_valid_2 (1'b0),
|
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.riu_prsnt_2 (1'b0),
|
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.riu_rddata_3 (16'b0),
|
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.riu_valid_3 (1'b0),
|
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.riu_prsnt_3 (1'b0),
|
||||
.rx_btval_1 (),
|
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.rx_btval_2 (),
|
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.rx_btval_3 (),
|
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.tx_dly_rdy_1 (1'b1),
|
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.rx_dly_rdy_1 (1'b1),
|
||||
.rx_vtc_rdy_1 (1'b1),
|
||||
.tx_vtc_rdy_1 (1'b1),
|
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.tx_dly_rdy_2 (1'b1),
|
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.rx_dly_rdy_2 (1'b1),
|
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.rx_vtc_rdy_2 (1'b1),
|
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.tx_vtc_rdy_2 (1'b1),
|
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.tx_dly_rdy_3 (1'b1),
|
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.rx_dly_rdy_3 (1'b1),
|
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.rx_vtc_rdy_3 (1'b1),
|
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.tx_vtc_rdy_3 (1'b1),
|
||||
.tx_rdclk_out ()
|
||||
);
|
||||
|
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wire phy_mdio_i;
|
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wire phy_mdio_o;
|
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wire phy_mdio_t;
|
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assign phy_mdio_i = phy_mdio;
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||||
assign phy_mdio = phy_mdio_t ? 1'bz : phy_mdio_o;
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||||
|
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wire [7:0] led_int;
|
||||
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// SGMII interface debug:
|
||||
// SW12:1 (sw[3]) off for payload byte, on for status vector
|
||||
// SW12:4 (sw[0]) off for LSB of status vector, on for MSB
|
||||
assign led = sw[3] ? (sw[0] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btnu(btnu_int),
|
||||
.btnl(btnl_int),
|
||||
.btnd(btnd_int),
|
||||
.btnr(btnr_int),
|
||||
.btnc(btnc_int),
|
||||
.sw(sw_int),
|
||||
.led(led_int),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rts(uart_rts),
|
||||
.uart_cts(uart_cts_int),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T SGMII
|
||||
*/
|
||||
.phy_gmii_clk(phy_gmii_clk_int),
|
||||
.phy_gmii_rst(phy_gmii_rst_int),
|
||||
.phy_gmii_clk_en(phy_gmii_clk_en_int),
|
||||
.phy_gmii_rxd(phy_gmii_rxd_int),
|
||||
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
||||
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
||||
.phy_gmii_txd(phy_gmii_txd_int),
|
||||
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
||||
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
||||
.phy_reset_n(phy_reset_n),
|
||||
.phy_int_n(phy_int_n),
|
||||
.phy_mdio_i(phy_mdio_i),
|
||||
.phy_mdio_o(phy_mdio_o),
|
||||
.phy_mdio_t(phy_mdio_t),
|
||||
.phy_mdc(phy_mdc),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp1_tx_p(qsfp1_tx_p),
|
||||
.qsfp1_tx_n(qsfp1_tx_n),
|
||||
.qsfp1_rx_p(qsfp1_rx_p),
|
||||
.qsfp1_rx_n(qsfp1_rx_n),
|
||||
.qsfp1_mgt_refclk_0_p(qsfp1_mgt_refclk_0_p),
|
||||
.qsfp1_mgt_refclk_0_n(qsfp1_mgt_refclk_0_n),
|
||||
// .qsfp1_mgt_refclk_1_p(qsfp1_mgt_refclk_1_p),
|
||||
// .qsfp1_mgt_refclk_1_n(qsfp1_mgt_refclk_1_n),
|
||||
// .qsfp1_recclk_p(qsfp1_recclk_p),
|
||||
// .qsfp1_recclk_n(qsfp1_recclk_n),
|
||||
.qsfp1_modsell(qsfp1_modsell),
|
||||
.qsfp1_resetl(qsfp1_resetl),
|
||||
.qsfp1_modprsl(qsfp1_modprsl),
|
||||
.qsfp1_intl(qsfp1_intl),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
.qsfp2_tx_p(qsfp2_tx_p),
|
||||
.qsfp2_tx_n(qsfp2_tx_n),
|
||||
.qsfp2_rx_p(qsfp2_rx_p),
|
||||
.qsfp2_rx_n(qsfp2_rx_n),
|
||||
// .qsfp2_mgt_refclk_0_p(qsfp2_mgt_refclk_0_p),
|
||||
// .qsfp2_mgt_refclk_0_n(qsfp2_mgt_refclk_0_n),
|
||||
// .qsfp2_mgt_refclk_1_p(qsfp2_mgt_refclk_1_p),
|
||||
// .qsfp2_mgt_refclk_1_n(qsfp2_mgt_refclk_1_n),
|
||||
// .qsfp2_recclk_p(qsfp2_recclk_p),
|
||||
// .qsfp2_recclk_n(qsfp2_recclk_n),
|
||||
.qsfp2_modsell(qsfp2_modsell),
|
||||
.qsfp2_resetl(qsfp2_resetl),
|
||||
.qsfp2_modprsl(qsfp2_modprsl),
|
||||
.qsfp2_intl(qsfp2_intl),
|
||||
.qsfp2_lpmode(qsfp2_lpmode)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user